Alpha EV5 events

This is a list of Alpha EV5 CPU's performance counter event types. Please see alpha architecture reference

Name	Description	Counters usable	Unit mask options
CYCLES	Total cycles	0, 2
ISSUES	Total issues	0
NON_ISSUE_CYCLES	Nothing issued, pipeline frozen	1
SPLIT_ISSUE_CYCLES	Some but not all issuable instructions issued	1
PIPELINE_DRY	Nothing issued, pipeline dry	1
REPLAY_TRAP	Replay traps (ldu, wb/maf, litmus test)	1
SINGLE_ISSUE_CYCLES	Single issue cycles	1
DUAL_ISSUE_CYCLES	Dual issue cycles	1
TRIPLE_ISSUE_CYCLES	Triple issue cycles	1
QUAD_ISSUE_CYCLES	Quad issue cycles	1
FLOW_CHANGE	Flow change (meaning depends on counter 2)	1
INTEGER_OPERATE	Integer operate instructions	1
FP_INSNS	FP operate instructions (not br, load, store)	1
LOAD_INSNS	Load instructions	1
STORE_INSNS	Store instructions	1
ICACHE_ACCESS	Data cache access	1
LONG_STALLS	Stalls longer than 15 cycles	2
PC_MISPR	PC mispredicts	2
BRANCH_MISPREDICTS	Branch mispredicts	2
ICACHE_MISSES	Instruction cache misses	2
ITB_MISS	Instruction TLB miss	2
DCACHE_MISSES	Data cache misses	2
DTB_MISS	Data TLB miss	2
LOADS_MERGED	Loads merged in MAF	2
LDU_REPLAYS	LDU replay traps	2
WB_MAF_FULL_REPLAYS	WB/MAF full replay traps	2
MEM_BARRIER	Memory barrier instructions	2
LOAD_LOCKED	LDx/L instructions	2
SCACHE_ACCESS	S-cache access	1
SCACHE_READ	S-cache read	1
SCACHE_WRITE	S-cache write	1, 2
SCACHE_VICTIM	S-cache victim	1
SCACHE_MISS	S-cache miss	2
SCACHE_READ_MISS	S-cache read miss	2
SCACHE_WRITE_MISS	S-cache write miss	2
SCACHE_SH_WRITE	S-cache shared writes	2
BCACHE_HIT	B-cache hit	1
BCACHE_VICTIM	B-cache victim	1
BCACHE_MISS	B-cache miss	2
SYS_REQ	System requests	1
SYS_INV	System invalidates	2
SYS_READ_REQ	System read requests	2