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Alpha EV67 events

This is a list of Alpha EV67 CPU's performance counter event types. Please see alpha architecture reference

NameDescriptionCounters usableUnit mask options
CYCLES Total cycles 0
DELAYED_CYCLES Cycles of delayed retire pointer advance 1
RETIRED Retired instructions 0, 1
BCACHE_MISS Bcache misses/long probe latency 1
MBOX_REPLAY Mbox replay traps 1
STALLED_0 PCTR0 triggered; stalled between fetch and map stages 0
TAKEN_0 PCTR0 triggered; branch was not mispredicted and taken 0
MISPREDICT_0 PCTR0 triggered; branch was mispredicted 0
ITB_MISS_0 PCTR0 triggered; ITB miss 0
DTB_MISS_0 PCTR0 triggered; DTB miss 0
REPLAY_0 PCTR0 triggered; replay trap 0
LOAD_STORE_0 PCTR0 triggered; load-store order replay trap 0
ICACHE_MISS_0 PCTR0 triggered; Icache miss 0
UNALIGNED_0 PCTR0 triggered; unaligned load/store trap 0
STALLED_1 PCTR1 triggered; stalled between fetch and map stages 0
TAKEN_1 PCTR1 triggered; branch was not mispredicted and taken 0
MISPREDICT_1 PCTR1 triggered; branch was mispredicted 0
ITB_MISS_1 PCTR1 triggered; ITB miss 0
DTB_MISS_1 PCTR1 triggered; DTB miss 0
REPLAY_1 PCTR1 triggered; replay trap 0
LOAD_STORE_1 PCTR1 triggered; load-store order replay trap 0
ICACHE_MISS_1 PCTR1 triggered; Icache miss 0
UNALIGNED_1 PCTR1 triggered; unaligned load/store trap 0
It is a capital mistake to theorise before one has data. Insensibly one begins to twist facts to suit theories instead of theories to suit facts. - Sherlock Holmes
2013/07/29