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AMD family 14h events

This is a list of AMD64 family 14h's CPU's performance counter event types. Please see BIOS and Kernel Developer's Guide for AMD Family 14h Processors.

NameDescriptionCounters usableUnit mask options
DISPATCHED_FPU_OPS Dispatched FPU Operations all 0x01: Pipe0 (fadd, imul, mmx) ops
0x02: Pipe1 (fmul, store, mmx) ops
0x03: All ops
CYCLES_FPU_EMPTY Cycles in which the FPU is Empty all
DISPATCHED_FPU_OPS_FAST_FLAG Dispatched Fast Flag FPU Operations all
RETIRED_SSE_OPS Retired SSE Operations all 0x01: Single Precision add/subtract ops
0x02: Single precision multiply ops
0x04: Single precision divide/square root ops
0x08: Double precision add/subtract ops
0x10: Double precision multiply ops
0x20: Double precision divide/square root ops
0x40: OP type: 0=uops 1=FLOPS
RETIRED_MOVE_OPS Retired Move Ops all 0x04: All other merging move uops
0x08: All other move uops
RETIRED_SERIALIZING_OPS Retired Serializing Ops all 0x01: SSE bottom-executing uops retired
0x02: SSE bottom-serializing uops retired
0x04: x87 bottom-executing uops retired
0x08: x87 bottom-serializing uops retired
RETIRED_X87_FP_OPS Retired x87 Floating Point Operations all 0x01: Add/subtract ops
0x02: Multiply ops
0x04: Divide and FSQRT ops
SEGMENT_REGISTER_LOADS Segment Register Loads all 0x01: ES register
0x02: CS register
0x04: SS register
0x08: DS register
0x10: FS register
0x20: GS register
0x40: HS register
PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE Pipeline Restart Due to Self-Modifying Code all
PIPELINE_RESTART_DUE_TO_PROBE_HIT Pipeline Restart Due to Probe Hit all
RSQ_FULL RSQ Full all
LOCKED_OPS Locked Operations all 0x01: Number of locked instructions executed
0x02: Number cycles to acquire bus lock
0x04: Number of cycles to unlock cache line (not including cache miss)
RETIRED_CLFLUSH_INSTRUCTIONS Retired CLFLUSH Instructions all
RETIRED_CPUID_INSTRUCTIONS Retired CPUID Instructions all
CANCELLED_STORE_TO_LOAD Store to Load Forward Operations Block Loads all 0x01: Address mismatches (starting byte not the same)
0x02: Store is smaller than load
0x04: Misaligned
DATA_CACHE_ACCESSES Data Cache Accesses all
DATA_CACHE_MISSES Data Cache Misses all
DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE Data Cache Refills from L2 or Northbridge all 0x01: Non-cacheable return of data
0x02: Shared
0x04: Exclusive
0x08: Owned
0x10: Modified
0x1e: All cache states except non-cacheable
DATA_CACHE_REFILLS_FROM_NORTHBRIDGE Data Cache Refills from the northbridge all 0x01: Non-cacheable read data
0x02: Shared
0x04: Exclusive
0x08: Owned
0x10: Modified
0x1f: All cache states
DATA_CACHE_LINES_EVICTED Data Cache Lines Evicted all 0x01: Evicted from probe
0x02: Shared eviction
0x04: Exclusive eviction
0x08: Owned eviction
0x10: Modified eviction
L1_DTLB_MISS_AND_L2_DTLB_HIT L1 DTLB Miss and L2 DTLB Hit all
DTLB_MISS DTLB Miss all 0x01: Count stores that miss L1TLB
0x02: Count loads that miss L1TLB
0x04: Count stores that miss L2TLB
0x08: Count loads that miss L2TLB
MISALIGNED_ACCESSES Misaligned Accesses all
PREFETCH_INSTRUCTIONS_DISPATCHED Prefetch Instructions Dispatched all 0x01: Load (Prefetch, PrefetchT0/T1/T2)
0x02: Store (PrefetchW)
0x04: NTA (PrefetchNTA)
LOCKED_INSTRUCTIONS_DCACHE_MISSES DCACHE Misses by Locked Instructions all
L1_DTLB_HIT L1 DTLB Hit all 0x01: L1 4K TLB hit
0x02: L1 2M TLB hit
INEFFECTIVE_SW_PREFETCHES DCACHE Ineffective Software Prefetches all 0x01: Software prefetch hit in the data cache
0x02: Software prefetch hit a pending fill
0x04: Software prefetches that don't get a MAB
0x08: Software prefetch hit in L2
GLOBAL_TLB_FLUSHES Global Page Invalidations all
MEMORY_REQUESTS Memory Requests by Type all 0x01: Requests to non-cacheable (UC) memory
0x02: Requests to write-combining (WC) memory
0x80: Streaming store (SS) requests
MAB_REQS MAB Requests all 0x00: DC miss buffer 0
0x01: DC miss buffer 1
0x02: DC miss buffer 2
0x03: DC miss buffer 3
0x04: DC miss buffer 4
0x05: DC miss buffer 5
0x06: DC miss buffer 6
0x07: DC miss buffer 7
0x08: IC miss buffer 0
0x09: IC miss buffer 1
0x0a: Any DC miss buffer
0x0b: Any IC miss buffer
MAB_WAIT MAB Wait Cycles all 0x00: DC miss buffer 0
0x01: DC miss buffer 1
0x02: DC miss buffer 2
0x03: DC miss buffer 3
0x04: DC miss buffer 4
0x05: DC miss buffer 5
0x06: DC miss buffer 6
0x07: DC miss buffer 7
0x08: IC miss buffer 0
0x09: IC miss buffer 1
0x0a: Any DC miss buffer
0x0b: Any IC miss buffer
NORTHBRIDGE_READ_RESPONSES System Response by Coherence State all 0x01: Exclusive
0x02: Modified
0x04: Shared
0x08: Owned
0x10: Data Error
0x20: Change-to-Dirty success
0x40: Uncacheable
CPU_CLK_UNHALTED CPU Clocks not Halted all
REQUESTS_TO_L2 Requests to L2 Cache all 0x01: IC fill
0x02: DC fill
0x08: Tag snoop request
L2_CACHE_MISS L2 Cache Misses all 0x01: IC fill
0x02: DC fill
L2_CACHE_FILL_WRITEBACK L2 Fill/Writeback all 0x01: L2 fills (victims from L1 caches)
0x02: L2 writebacks to system
0x04: IC attribute writes which access the L2
0x08: IC attribute writes which store into the L2
PDC_MISS PDC Miss all 0x01: Host: PDE Level
0x02: Host: PDPE Level
0x04: Host: PML4E Level
0x10: Guest: PDE Level
0x20: Guest: PDPE Level
0x40: Guest: PML4E Level
INSTRUCTION_CACHE_FETCHES Instruction Cache Fetches all
INSTRUCTION_CACHE_MISSES Instruction Cache Misses all
INSTRUCTION_CACHE_REFILLS_FROM_L2 Instruction Cache Refills from L2 all
INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM Instruction Cache Refills from System all
ITLB_MISS ITLB Miss all 0x01: Instruction fetches to a 4K page
0x02: Instruction fetches to a 2M page
INSTRUCTION_FETCH_STALL Instruction Fetch Stall all
RETURN_STACK_HITS Return Stack Hits all
RETURN_STACK_OVERFLOWS Return Stack Overflows all
INSTRUCTION_CACHE_VICTIMS Instruction Cache Victims all
INSTRUCTION_CACHE_INVALIDATED Instruction Cache Lines Invalidated all 0x01: IC invalidate due to an LS probe
0x02: IC invalidate due to a BU probe
ITLB_RELOADS ITLB Reloads all
ITLB_RELOADS_ABORTED ITLB Reloads Aborted all
RETIRED_INSTRUCTIONS Retired Instructions all
RETIRED_UOPS Retired uops all
RETIRED_BRANCH_INSTRUCTIONS Retired Branch Instructions all
RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS Retired Mispredicted Branch Instructions all
RETIRED_TAKEN_BRANCH_INSTRUCTIONS Retired Taken Branch Instructions all
RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED Retired Taken Branch Instructions Mispredicted all
RETIRED_FAR_CONTROL_TRANSFERS Retired Far Control Transfers all
RETIRED_BRANCH_RESYNCS Retired Branch Resyncs all
RETIRED_NEAR_RETURNS Retired Near Returns all
RETIRED_NEAR_RETURNS_MISPREDICTED Retired Near Returns Mispredicted all
RETIRED_INDIRECT_BRANCHES_MISPREDICTED Retired Mispredicted Taken Branch Instructions due to Target Mismatch all
RETIRED_MMX_FP_INSTRUCTIONS Retired a Floating Point Instruction all 0x01: x87 or MMX(tm) instruction was retired
0x02: SSE floating point instruction was retired (SSE, SSE2, SSE3, MNI)
INTERRUPTS_MASKED_CYCLES Interrupts-Masked Cycles all
INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING Interrupts-Masked Cycles with Interrupt Pending all
INTERRUPTS_TAKEN Interrupts Taken all
FPU_EXCEPTIONS FPU Exceptions all 0x01: x87 reclass microfaults
0x02: SSE retype microfaults
0x04: SSE reclass microfaults
0x08: SSE and x87 microtraps
DR0_BREAKPOINTS DR0 Breakpoint Matches all
DR1_BREAKPOINTS DR1 Breakpoint Matches all
DR2_BREAKPOINTS DR2 Breakpoint Matches all
DR3_BREAKPOINTS DR3 Breakpoint Matches all
DRAM_ACCESSES DRAM Accesses all 0x01: DCT0 Page Hit
0x02: DCT0 Page Miss
0x04: DCT0 Page Conflict
0x40: Write request
0x80: Read request
DCT0_PAGE_TABLE_EVENTS DRAM Controller Page Table Events all 0x01: DCT0 Page Table Overflow
0x02: DCT0 Number of stale table entry hits
0x04: DCT0 Page table idle cycle limit incremented
0x08: DCT0 Page table idle cycle limit decremented
0x10: DCT0 Page table is closed due to row inactivity
MEMORY_CONTROLLER_SLOT_MISSED Memory Controller DRAM Command Slots Missed all 0x10: DCT0 RBD
0x40: DCT0 Prefetch
MEMORY_CONTROLLER_TURNAROUNDS Memory Controller Turnarounds all 0x01: DCT0 read-to-write turnaround
0x02: DCT0 write-to-read turnaround
MEMORY_CONTROLLER_RBD_QUEUE_EVENTS Memory Controller RBD Queue Events all 0x04: D18F2x94[DcqBypassMax] counter reached
0x08: Bank closed due to conflict with outstanding request in RBD queue
THERMAL_STATUS Thermal Status all 0x01: MEMHOT_L assertions
0x04: Number of times the HTC transitions from inactive to active
0x20: Number of clocks HTC P-state is inactive
0x40: Number of clocks HTC P-state is active
0x80: PROCHOT_L asserted by external source and caused P-state change
CPU_IO_REQUESTS_TO_MEMORY_IO CPU/IO Requests to Memory/IO all 0x01: IO to IO
0x02: IO to Mem
0x04: CPU to IO
0x08: CPU to Mem
CACHE_BLOCK_COMMANDS Cache Block Commands all 0x01: Victim Block (Writeback)
0x04: Read Block (Dcache load miss refill)
0x08: Read Block Shared (Icache refill)
0x10: Read Block Modified (Dcache store miss refill)
0x20: Change-to-Dirty (first store to clean block already in cache)
SIZED_COMMANDS Sized Commands all 0x01: Non-Posted SzWr Byte (1-32 bytes)
0x02: Non-Posted SzWr DW (1-16 doublewords)
0x04: Posted SzWr Byte (1-32 bytes)
0x08: Posted SzWr DW (1-16 doublewords)
0x10: SzRd Byte (4 bytes)
0x20: SzRd DW (1-16 doublewords)
PROBE_RESPONSES_AND_UPSTREAM_REQUESTS Probe Responses and Upstream Requests all 0x01: Probe miss
0x02: Probe hit clean
0x04: Probe hit dirty without memory cancel
0x08: Probe hit dirty with memory cancel
0x10: Upstream high priority reads
0x20: Upstream low priority reads
0x80: Upstream low priority writes
DEV_EVENTS DEV Events all 0x10: DEV hit
0x20: DEV miss
0x40: DEV error
MEMORY_CONTROLLER_REQUESTS Memory Controller Requests all 0x08: 32 Bytes Sized Writes
0x10: 64 Bytes Sized Writes
0x20: 32 Bytes Sized Reads
0x40: 64 Byte Sized Reads
SIDEBAND_SIGNALS Sideband Signals and Special Cycles all 0x02: STOPGRANT
0x04: SHUTDOWN
0x08: WBINVD
0x10: INVD
INTERRUPT_EVENTS Interrupt Events all 0x01: Fixed and LPA
0x02: LPA
0x04: SMI
0x08: NMI
0x10: INIT
0x20: STARTUP
0x40: INT
0x80: EOI
IBS_FETCH_ALL All IBS fetch samples ibs_fetch
IBS_FETCH_KILLED IBS fetch killed ibs_fetch
IBS_FETCH_ATTEMPTED IBS fetch attempted ibs_fetch
IBS_FETCH_COMPLETED IBS fetch completed ibs_fetch
IBS_FETCH_ABORTED IBS fetch aborted ibs_fetch
IBS_FETCH_ITLB_HITS IBS ITLB hit ibs_fetch
IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_HITS IBS L1 ITLB misses (and L2 ITLB hits) ibs_fetch
IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_MISSES IBS L1 L2 ITLB miss ibs_fetch
IBS_FETCH_ICACHE_MISSES IBS instruction cache misses ibs_fetch
IBS_FETCH_ICACHE_HITS IBS instruction cache hit ibs_fetch
IBS_FETCH_4K_PAGE IBS 4K page translation ibs_fetch
IBS_FETCH_2M_PAGE IBS 2M page translation ibs_fetch
IBS_FETCH_LATENCY IBS fetch latency ibs_fetch
IBS_OP_ALL All IBS op samples ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_TAG_TO_RETIRE IBS tag-to-retire cycles ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_COMP_TO_RET IBS completion-to-retire cycles ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_BRANCH_RETIRED IBS branch op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_MISPREDICTED_BRANCH IBS mispredicted branch op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_TAKEN_BRANCH IBS taken branch op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_MISPREDICTED_BRANCH_TAKEN IBS mispredicted taken branch op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_RETURNS IBS return op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_MISPREDICTED_RETURNS IBS mispredicted return op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_RESYNC IBS resync op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_ALL_LOAD_STORE IBS all load store ops ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_LOAD IBS load ops ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_STORE IBS store ops ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L1_DTLB_HITS IBS L1 DTLB hit ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L1_DTLB_MISS_L2_DTLB_HIT IBS L1 DTLB misses L2 hits ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L1_L2_DTLB_MISS IBS L1 and L2 DTLB misses ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_DATA_CACHE_MISS IBS data cache misses ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_DATA_HITS IBS data cache hits ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_MISALIGNED_DATA_ACC IBS misaligned data access ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_BANK_CONF_LOAD IBS bank conflict on load op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_BANK_CONF_STORE IBS bank conflict on store op ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_FORWARD IBS store-to-load forwarded ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_CANCELLED IBS store-to-load cancelled ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_DCUC_MEM_ACC IBS UC memory access ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_DCWC_MEM_ACC IBS WC memory access ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_LOCKED IBS locked operation ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_MAB_HIT IBS MAB hit ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L1_DTLB_4K IBS L1 DTLB 4K page ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L1_DTLB_2M IBS L1 DTLB 2M page ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L1_DTLB_1G IBS L1 DTLB 1G page ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L2_DTLB_4K IBS L2 DTLB 4K page ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L2_DTLB_2M IBS L2 DTLB 2M page ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_L2_DTLB_1G IBS L2 DTLB 1G page ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_DC_LOAD_LAT IBS data cache miss load latency ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_LOCAL_ONLY IBS Northbridge local ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_REMOTE_ONLY IBS Northbridge remote ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_LOCAL_L3 IBS Northbridge local L3 ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_LOCAL_CACHE IBS Northbridge local core L1 or L2 cache ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_REMOTE_CACHE IBS Northbridge local core L1, L2, L3 cache ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_LOCAL_DRAM IBS Northbridge local DRAM ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_REMOTE_DRAM IBS Northbridge remote DRAM ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_LOCAL_OTHER IBS Northbridge local APIC MMIO Config PCI ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_REMOTE_OTHER IBS Northbridge remote APIC MMIO Config PCI ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_CACHE_MODIFIED IBS Northbridge cache modified state ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_CACHE_OWNED IBS Northbridge cache owned state ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_LOCAL_CACHE_LAT IBS Northbridge local cache latency ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
IBS_OP_NB_REMOTE_CACHE_LAT IBS Northbridge remote cache latency ibs_op 0x00: Using IBS OP cycle count mode
0x01: Using IBS OP dispatch count mode
0x02: Enable IBS OP Memory Access Log
0x04: Enable IBS OP Branch Target Address Log
It is a capital mistake to theorise before one has data. Insensibly one begins to twist facts to suit theories instead of theories to suit facts. - Sherlock Holmes
2013/07/29