AMD events

This is a list of AMD64 processors CPU's performance counter event types. Please see the AMD Optimization Manual for more details. Note that any counter can be used for any event.

Name	Description	Counters usable	Unit mask options
CPU_CLK_UNHALTED	Cycles outside of halt state	all
RETIRED_INSTRUCTIONS	Retired instructions (includes exceptions, interrupts, re-syncs)	all
RETIRED_UOPS	Retired micro-ops	all
INSTRUCTION_CACHE_FETCHES	Instruction cache fetches (RevE)	all
INSTRUCTION_CACHE_MISSES	Instruction cache misses	all
DATA_CACHE_ACCESSES	Data cache accesses	all
DATA_CACHE_MISSES	Data cache misses	all
DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM	Data cache refills from L2 or system	all	0x10: (M)odified cache state 0x08: (O)wner cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: refill from system 0x1e: All cache states except Invalid
DATA_CACHE_REFILLS_FROM_SYSTEM	Data cache refills from system	all	0x10: (M)odified cache state 0x08: (O)wner cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x1f: All cache states
DATA_CACHE_LINES_EVICTED	Data cache lines evicted	all	0x10: (M)odified cache state 0x08: (O)wner cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x1f: All cache states
RETIRED_BRANCH_INSTRUCTIONS	Retired branches (conditional, unconditional, exceptions, interrupts)	all
RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS	Retired Mispredicted Branch Instructions	all
RETIRED_TAKEN_BRANCH_INSTRUCTIONS	Retired taken branch instructions	all
RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED	Retired taken branches mispredicted	all
L1_DTLB_MISS_AND_L2_DTLB_HIT	L1 DTLB misses and L2 DTLB hits	all
L1_DTLB_AND_L2_DTLB_MISS	L1 and L2 DTLB misses	all
MISALIGNED_ACCESSES	Misaligned Accesses	all
L1_ITLB_MISS_AND_L2_ITLB_HIT	L1 ITLB misses (and L2 ITLB hits)	all
L1_ITLB_MISS_AND_L2_ITLB_MISS	L1 ITLB Miss, L2 ITLB Miss	all
RETIRED_FAR_CONTROL_TRANSFERS	Retired far control transfers	all
RETIRED_BRANCH_RESYNCS	Retired branches resyncs (only non-control transfer branches)	all
INTERRUPTS_MASKED_CYCLES	Cycles with interrupts masked (IF=0)	all
INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING	Cycles with interrupts masked while interrupt pending	all
INTERRUPTS_TAKEN	Number of taken hardware interrupts	all
DISPATCHED_FPU_OPS	Dispatched FPU ops	all	0x01: Add pipe ops 0x02: Multiply pipe 0x04: Store pipe ops 0x08: Add pipe load ops 0x10: Multiply pipe load ops 0x20: Store pipe load ops
CYCLES_NO_FPU_OPS_RETIRED	Cycles with no FPU ops retired	all
DISPATCHED_FPU_OPS_FAST_FLAG	Dispatched FPU ops that use the fast flag interface	all
SEGMENT_REGISTER_LOADS	Segment register loads	all	0x01: ES register 0x02: CS register 0x04: SS register 0x08: DS register 0x10: FS register 0x20: GS register 0x40: HS register
PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE	Micro-architectural re-sync caused by self modifying code	all
PIPELINE_RESTART_DUE_TO_PROBE_HIT	Micro-architectural re-sync caused by snoop	all
LS_BUFFER_2_FULL_CYCLES	Cycles LS Buffer 2 Full	all
LOCKED_OPS	Locked operations	all	0x01: The number of locked instructions executed 0x02: The number of cycles spent in speculative phase 0x04: The number of cycles spent in non-speculative phase (including cache miss penalty)
OP_LATE_CANCEL	Micro-architectural late cancel of an operation	all
RETIRED_CLFLUSH_INSTRUCTIONS	Retired CLFLUSH instructions	all
RETIRED_CPUID_INSTRUCTIONS	Retired CPUID instructions	all
MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS	Micro-architectural late cancel of an access	all
MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS	Micro-architectural early cancel of an access	all
SCRUBBER_SINGLE_BIT_ECC_ERRORS	One bit ECC error recorded by scrubber	all	0x01: Scrubber error 0x02: Piggyback scrubber errors
PREFETCH_INSTRUCTIONS_DISPATCHED	Prefetch Instructions Dispatched	all	0x01: Load 0x02: Store 0x04: NTA
DCACHE_MISS_LOCKED_INSTRUCTIONS	DCACHE Misses by Locked Instructions	all	0x02: Data Cache Misses by Locked Instructions
MEMORY_REQUESTS	Memory Requests by Type	all	0x01: Requests to non-cacheable (UC) memory 0x02: Requests to write-combining (WC) memory or WC buffer flushes to WB memory 0x80: Streaming store (SS) requests
DATA_PREFETCHES	Data Prefetcher	all	0x01: Cancelled prefetches 0x02: Prefetch attempts
SYSTEM_READ_RESPONSES	System Read Responses by Coherency State	all	0x01: Exclusive 0x02: Modified 0x04: Shared
QUADWORD_WRITE_TRANSFERS	Quadwords Written to System	all
REQUESTS_TO_L2	Requests to L2 Cache	all	0x01: IC fill 0x02: DC fill 0x04: TLB reload 0x08: Tag snoop request 0x10: Canceled request
L2_CACHE_MISS	L2 Cache Misses	all	0x01: IC fill 0x02: DC fill 0x04: TLB reload
L2_CACHE_FILL_WRITEBACK	L2 Fill/Writeback	all	0x01: L2 fills (victims from L1 caches, TLB page table walks and data prefetches) 0x02: L2 Writebacks to system
INSTRUCTION_CACHE_REFILLS_FROM_L2	Instruction Cache Refills from L2	all
INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM	Instruction Cache Refills from System	all
PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE	Pipeline Restart Due to Instruction Stream Probe	all
INSTRUCTION_FETCH_STALL	Instruction fetch stall	all
RETURN_STACK_HITS	Return stack hit	all
RETURN_STACK_OVERFLOWS	Return stack overflow	all
RETIRED_NEAR_RETURNS	Retired near returns	all
RETIRED_NEAR_RETURNS_MISPREDICTED	Retired near returns mispredicted	all
RETIRED_INDIRECT_BRANCHES_MISPREDICTED	Retired Indirect Branches Mispredicted	all
RETIRED_MMX_FP_INSTRUCTIONS	Retired MMX/FP instructions	all	0x01: x87 instructions 0x02: Combined MMX & 3DNow instructions 0x04: Combined packed SSE & SSE2 instructions 0x08: Combined packed scalar SSE & SSE2 instructions
RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS	Retired FastPath double-op instructions	all	0x01: With low op in position 0 0x02: With low op in position 1 0x04: With low op in position 2
DECODER_EMPTY	Nothing to dispatch (decoder empty)	all
DISPATCH_STALLS	Dispatch stalls	all
DISPATCH_STALL_FOR_BRANCH_ABORT	Dispatch stall from branch abort to retire	all
DISPATCH_STALL_FOR_SERIALIZATION	Dispatch stall for serialization	all
DISPATCH_STALL_FOR_SEGMENT_LOAD	Dispatch stall for segment load	all
DISPATCH_STALL_FOR_REORDER_BUFFER_FULL	Dispatch stall for reorder buffer full	all
DISPATCH_STALL_FOR_RESERVATION_STATION_FULL	Dispatch stall when reservation stations are full	all
DISPATCH_STALL_FOR_FPU_FULL	Dispatch stall when FPU is full	all
DISPATCH_STALL_FOR_LS_FULL	Dispatch stall when LS is full	all
DISPATCH_STALL_WAITING_FOR_ALL_QUIET	Dispatch stall when waiting for all to be quiet	all
DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC	Dispatch Stall for Far Transfer or Resync to Retire	all
FPU_EXCEPTIONS	FPU exceptions	all	0x01: x87 reclass microfaults 0x02: SSE retype microfaults 0x04: SSE reclass microfaults 0x08: SSE and x87 microtraps
DR0_BREAKPOINTS	Number of breakpoints for DR0	all
DR1_BREAKPOINTS	Number of breakpoints for DR1	all
DR2_BREAKPOINTS	Number of breakpoints for DR2	all
DR3_BREAKPOINTS	Number of breakpoints for DR3	all
DRAM_ACCESSES	DRAM Accesses	all	0x01: Page hit 0x02: Page miss 0x04: Page conflict
MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS	Memory controller page table overflows	all
MEMORY_CONTROLLER_TURNAROUNDS	Memory controller turnarounds	all	0x01: DIMM (chip select) turnaround 0x02: Read to write turnaround 0x04: Write to read turnaround
MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION	Memory controller bypass saturation	all	0x01: Memory controller high priority bypass 0x02: Memory controller low priority bypass 0x04: DRAM controller interface bypass 0x08: DRAM controller queue bypass
THERMAL_STATUS_AND_DRAM_ECC_ERRORS	Thermal status and ECC errors	all	0x01: Number of clocks CPU is active when HTC is active 0x02: Number of clocks CPU clock is inactive when HTC is active 0x04: Number of clocks when die temperature is higher than the software high temperature threshold 0x08: Number of clocks when high temperature threshold was exceeded 0x80: Number of correctable and uncorrectable DRAM ECC errors
GART_EVENTS	GART Events	all	0x01: GART aperture hit on access from CPU 0x02: GART aperture hit on access from I/O 0x04: GART miss
SIZED_BLOCKS	Sized Blocks	all	0x04: 32-byte Sized Writes (RevD) 0x08: 64-byte Sized Writes (RevD) 0x10: 32-byte Sized Reads (RevD) 0x20: 64-byte Sized Reads (RevD)
CPU_IO_REQUESTS_TO_MEMORY_IO	CPU/IO Requests to Memory/IO (RevE)	all	0xa2: Requests Local I/O to Local Memory 0xa1: Requests Local I/O to Local I/O 0xa3: Requests Local I/O to Local Any 0xaa: Requests Local Any to Local Memory 0xa5: Requests Local Any to Local I/O 0xaf: Requests Local Any to Local Any 0x98: Requests Local CPU to Remote Memory 0x94: Requests Local CPU to Remote I/O 0x9c: Requests Local CPU to Remote Any 0x92: Requests Local I/O to Remote Memory 0x91: Requests Local I/O to Remote I/O 0x93: Requests Local I/O to Remote Any 0x9a: Requests Local Any to Remote Memory 0x95: Requests Local Any to Remote I/O 0x9f: Requests Local Any to Remote Any 0xb8: Requests Local CPU to Any Memory 0xb4: Requests Local CPU to Any I/O 0xbc: Requests Local CPU to Any Any 0xb2: Requests Local I/O to Any Memory 0xb1: Requests Local I/O to Any I/O 0xb3: Requests Local I/O to Any Any 0xba: Requests Local Any to Any Memory 0xb5: Requests Local Any to Any I/O 0xbf: Requests Local Any to Any Any 0x64: Requests Remote CPU to Local I/O 0x61: Requests Remote I/O to Local I/O 0x65: Requests Remote Any to Local I/O
CACHE_BLOCK_COMMANDS	Cache Block Commands (RevE)	all	0x01: Victim Block (Writeback) 0x04: Read Block (Dcache load miss refill) 0x08: Read Block Shared (Icache refill) 0x10: Read Block Modified (Dcache store miss refill) 0x20: Change to Dirty (first store to clean block already in cache)
SIZED_COMMANDS	Sized Commands	all	0x01: non-posted write byte 0x02: non-posted write dword 0x04: posted write byte 0x08: posted write dword 0x10: read byte (4 bytes) 0x20: read dword (1-16 dwords) 0x40: read-modify-write
PROBE_RESPONSES_AND_UPSTREAM_REQUESTS	Probe Responses and Upstream Requests	all	0x01: Probe miss 0x02: Probe hit clean 0x04: Probe hit dirty without memory cancel 0x08: Probe hit dirty with memory cancel 0x10: Upstream display refresh reads 0x20: Upstream non-display refresh reads 0x40: Upstream writes
HYPERTRANSPORT_LINK0_BANDWIDTH	HyperTransport(tm) link 0 bandwidth	all	0x01: Command sent 0x02: Data sent 0x04: Buffer release sent 0x08: NOP sent
HYPERTRANSPORT_LINK1_BANDWIDTH	HyperTransport(tm) link 1 bandwidth	all	0x01: Command sent 0x02: Data sent 0x04: Buffer release sent 0x08: NOP sent
HYPERTRANSPORT_LINK2_BANDWIDTH	HyperTransport(tm) link 2 bandwidth	all	0x01: Command sent 0x02: Data sent 0x04: Buffer release sent 0x08: NOP sent