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ARM MPCore events

This is a list of all ARM MPCore's performance counter event types. Please see ARM11 MPCore Processor Technical Reference Manual r1p0, Page 3-70, performance counters.

NameDescriptionCounters usableUnit mask options
IFU_IFETCH_MISS number of instruction fetch misses all
CYCLES_IFU_MEM_STALL cycles instruction fetch pipe is stalled all
CYCLES_DATA_STALL cycles stall occurs for due to data dependency all
ITLB_MISS number of ITLB misses all
DTLB_MISS number of DTLB misses all
BR_INST_EXECUTED branch instruction executed w/ or w/o program flow change all
BR_INST_NOT_PRED branch not predicted all
BR_INST_MISPRED branch mispredicted all
INSN_EXECUTED instruction executed all
INSN_FOLD_EXECUTED folded instruction executed all
DCACHE_ACCESS data cache read access all
DCACHE_MISS data cache miss all
DCACHE_WA data cache write access all
DCACHE_WM data cache write miss all
DCACHE_LINE_EV data cache line eviction all
SOFT_PC_CHANGE software changed PC without mode change all
TLB_MISS main TLB miss all
MEM_REQUEST external memory request (Cache request, write back) all
LS_QUEUE_FULL stall because load store unit queue being full all
LS_QUEUE_DRAINED number of times store buffer drained all
LS_QUEUE_WMERGE buffered write merged into a store buffer slot all
LS_SAFE_MODE LSU in safe mode all
CPU_CYCLES clock cycles counter all
Bottlenecks occur in surprising places, so don't try to second guess and put in a speed hack until you've proven that's where the bottleneck is. - Rob Pike