This is a list of all ARM V7 Krait's performance counter event types. Please see ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition Krait Processor Family Programmer's Reference Manual (PRM)
| Name | Description | Counters usable | Unit mask options |
| SW_INCR | Software increment of PMNC registers | 1, 2, 3, 4, 5, 6 | |
| L1I_CACHE_REFILL | Level 1 instruction cache refill | 1, 2, 3, 4, 5, 6 | |
| L1I_TLB_REFILL | Level 1 instruction TLB refill | 1, 2, 3, 4, 5, 6 | |
| L1D_CACHE_REFILL | Level 1 data cache refill | 1, 2, 3, 4, 5, 6 | |
| L1D_CACHE | Level 1 data cache access | 1, 2, 3, 4, 5, 6 | |
| L1D_TLB_REFILL | Level 1 data TLB refill | 1, 2, 3, 4, 5, 6 | |
| LD_RETIRED | Load instruction architecturally executed, condition code pass | 1, 2, 3, 4, 5, 6 | |
| ST_RETIRED | Store instruction architecturally executed, condition code pass | 1, 2, 3, 4, 5, 6 | |
| INST_RETIRED | Instruction architecturally executed | 1, 2, 3, 4, 5, 6 | |
| EXC_TAKEN | Exception taken | 1, 2, 3, 4, 5, 6 | |
| EXC_RETURN | Exception return instruction architecturally executed | 1, 2, 3, 4, 5, 6 | |
| CID_WRITE_RETIRED | Write to CONTEXTIDR register architecturally executed | 1, 2, 3, 4, 5, 6 | |
| PC_WRITE_RETIRED | Software change of the PC architecturally executed, condition code pass | 1, 2, 3, 4, 5, 6 | |
| BR_IMMED_RETIRED | Immediate branch instruction architecturally executed | 1, 2, 3, 4, 5, 6 | |
| BR_RETURN_RETIRED | Procedure return instruction architecturally executed, condition code pass | 1, 2, 3, 4, 5, 6 | |
| UNALIGNED_LDST_RETIRED | Unaligned load or store instruction architecturally executed, condition code pass | 1, 2, 3, 4, 5, 6 | |
| BR_MIS_PRED | Mispredicted or not predicted branch speculatively executed | 1, 2, 3, 4, 5, 6 | |
| BR_PRED | Predictable branch speculatively executed | 1, 2, 3, 4, 5, 6 | |
| MEM_ACCESS | Data memory access | 1, 2, 3, 4, 5, 6 | |
| L1I_CACHE | Level 1 instruction cache access | 1, 2, 3, 4, 5, 6 | |
| L1D_CACHE_WB | Level 1 data cache write-back | 1, 2, 3, 4, 5, 6 | |
| L2D_CACHE | Level 2 data cache access | 1, 2, 3, 4, 5, 6 | |
| L2D_CACHE_REFILL | Level 2 data cache refill | 1, 2, 3, 4, 5, 6 | |
| L2D_CACHE_WB | Level 2 data cache write-back | 1, 2, 3, 4, 5, 6 | |
| BUS_ACCESS | Bus access | 1, 2, 3, 4, 5, 6 | |
| MEMORY_ERROR | Local memory error | 1, 2, 3, 4, 5, 6 | |
| INST_SPEC | Instruction speculatively executed | 1, 2, 3, 4, 5, 6 | |
| TTBR_WRITE_RETIRED | Write to TTBR architecturally executed, condition code pass | 1, 2, 3, 4, 5, 6 | |
| BUS_CYCLES | Bus cycle | 1, 2, 3, 4, 5, 6 | |
| CPU_CYCLES | CPU cycle | 0 |
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