ARM V7 Scorpion events

This is a list of all ARM V7 Scorpion's performance counter event types. Please see ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition Scorpion Processor Family Programmer's Reference Manual (PRM)

Name	Description	Counters usable	Unit mask options
PMNC_SW_INCR	Software increment of PMNC registers	1, 2, 3, 4, 5, 6
IFETCH_MISS	Instruction fetch misses from cache or normal cacheable memory	1, 2, 3, 4, 5, 6
ITLB_MISS	Instruction fetch misses from TLB	1, 2, 3, 4, 5, 6
DCACHE_REFILL	Data R/W operation that causes a refill from cache or normal cacheable memory	1, 2, 3, 4, 5, 6
DCACHE_ACCESS	Data R/W from cache	1, 2, 3, 4, 5, 6
DTLB_REFILL	Data R/W that causes a TLB refill	1, 2, 3, 4, 5, 6
DREAD	Data read architecturally executed (note: architecturally executed = for instructions that are unconditional or that pass the condition code)	1, 2, 3, 4, 5, 6
DWRITE	Data write architecturally executed	1, 2, 3, 4, 5, 6
INSTR_EXECUTED	All executed instructions	1, 2, 3, 4, 5, 6
EXC_TAKEN	Exception taken	1, 2, 3, 4, 5, 6
EXC_EXECUTED	Exception return architecturally executed	1, 2, 3, 4, 5, 6
CID_WRITE	Instruction that writes to the Context ID Register architecturally executed	1, 2, 3, 4, 5, 6
PC_WRITE	SW change of PC, architecturally executed (not by exceptions)	1, 2, 3, 4, 5, 6
PC_IMM_BRANCH	Immediate branch instruction executed (taken or not)	1, 2, 3, 4, 5, 6
PC_PROC_RETURN	Procedure return architecturally executed (not by exceptions)	1, 2, 3, 4, 5, 6
UNALIGNED_ACCESS	Unaligned access architecturally executed	1, 2, 3, 4, 5, 6
PC_BRANCH_MIS_PRED	Branch mispredicted or not predicted. Counts pipeline flushes because of misprediction	1, 2, 3, 4, 5, 6
PC_BRANCH_MIS_USED	Branch or change in program flow that could have been predicted	1, 2, 3, 4, 5, 6
CPU_CYCLES	Number of CPU cycles	0
ICACHE_EXPL_INV	I-cache explicit invalidates	1, 2, 3, 4
ICACHE_MISS	I-cache misses	1, 2, 3, 4
ICACHE_ACCESS	I-cache accesses	1, 2, 3, 4
ICACHE_CACHEREQ_L2	I-cache cacheable requests to L2	1, 2, 3, 4
ICACHE_NOCACHE_L2	I-cache non-cacheable requests to L2	1, 2, 3, 4
HIQUP_NOPED	Conditional instructions HIQUPs NOPed	1, 2, 3, 4
DATA_ABORT	Interrupts and Exceptions Data Abort	1, 2, 3, 4
IRQ	Interrupts and Exceptions IRQ	1, 2, 3, 4
FIQ	Interrupts and Exceptions FIQ	1, 2, 3, 4
ALL_EXCPT	Interrupts and Exceptions All interrupts	1, 2, 3, 4
UNDEF	Interrupts and Exceptions Undefined	1, 2, 3, 4
SVC	Interrupts and Exceptions SVC	1, 2, 3, 4
SMC	Interrupts and Exceptions SMC	1, 2, 3, 4
PREFETCH_ABORT	Interrupts and Exceptions Prefetch Abort	1, 2, 3, 4
INDEX_CHECK	Interrupts and Exceptions Index Check	1, 2, 3, 4
NULL_CHECK	Interrupts and Exceptions Null Check	1, 2, 3, 4
EXPL_ICIALLU	I-cache and BTAC Invalidates Explicit ICIALLU	1, 2, 3, 4
IMPL_ICIALLU	I-cache and BTAC Invalidates Implicit ICIALLU	1, 2, 3, 4
NONICIALLU_BTAC_INV	I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate	1, 2, 3, 4
ICIMVAU_IMPL_ICIALLU	I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU	1, 2, 3, 4
SPIPE_ONLY_CYCLES	Issue S-pipe only issue cycles	1, 2, 3, 4
XPIPE_ONLY_CYCLES	Issue X-pipe only issue cycles	1, 2, 3, 4
DUAL_CYCLES	Issue dual issue cycles	1, 2, 3, 4
DISPATCH_ANY_CYCLES	Dispatch any dispatch cycles	1, 2, 3, 4
FIFO_FULLBLK_CMT	Commits Trace FIFO full Blk CMT	1, 2, 3, 4
FAIL_COND_INST	Conditional instructions failing conditional instrs (excluding branches)	1, 2, 3, 4
PASS_COND_INST	Conditional instructions passing conditional instrs (excluding branches)	1, 2, 3, 4
ALLOW_VU_CLK	Unit Clock Gating Allow VU Clks	1, 2, 3, 4
VU_IDLE	Unit Clock Gating VU Idle	1, 2, 3, 4
ALLOW_L2_CLK	Unit Clock Gating Allow L2 Clks	1, 2, 3, 4
L2_IDLE	Unit Clock Gating L2 Idle	1, 2, 3, 4
DTLB_IMPL_INV_SCTLR_DACR	DTLB implicit invalidates writes to SCTLR and DACR	1, 2, 3, 4
DTLB_EXPL_INV	DTLB explicit invalidates	1, 2, 3, 4
DTLB_MISS	DTLB misses	1, 2, 3, 4
DTLB_ACCESS	DTLB accesses	1, 2, 3, 4
ITLB_MISS	ITLB misses	1, 2, 3, 4
ITLB_IMPL_INV	ITLB implicit ITLB invalidates	1, 2, 3, 4
ITLB_EXPL_INV	ITLB explicit ITLB invalidates	1, 2, 3, 4
UTLB_D_MISS	UTLB d-side misses	1, 2, 3, 4
UTLB_D_ACCESS	UTLB d-side accesses	1, 2, 3, 4
UTLB_I_MISS	UTLB i-side misses	1, 2, 3, 4
UTLB_I_ACCESS	UTLB i-side accesses	1, 2, 3, 4
UTLB_INV_ASID	UTLB invalidate by ASID	1, 2, 3, 4
UTLB_INV_MVA	UTLB invalidate by MVA	1, 2, 3, 4
UTLB_INV_ALL	UTLB invalidate all	1, 2, 3, 4
S2_HOLD_RDQ_UNAVAIL	S2 hold RDQ unavail	1, 2, 3, 4
S2_HOLD	S2 hold S2 hold	1, 2, 3, 4
S2_HOLD_DEV_OP	S2 hold device op	1, 2, 3, 4
S2_HOLD_ORDER	S2 hold strongly ordered op	1, 2, 3, 4
S2_HOLD_BARRIER	S2 hold barrier	1, 2, 3, 4
SCORPION_VIU_DUAL_CYCLE	Scorpion VIU dual cycle	1, 2, 3, 4
SCORPION_VIU_SINGLE_CYCLE	Scorpion VIU single cycle	1, 2, 3, 4
SCORPION_VX_PIPE_WAR_STALL_CYCLES	Scorpion VX pipe WAR cycles	1, 2, 3, 4
SCORPION_VX_PIPE_WAW_STALL_CYCLES	Scorpion VX pipe WAW cycles	1, 2, 3, 4
SCORPION_VX_PIPE_RAW_STALL_CYCLES	Scorpion VX pipe RAW cycles	1, 2, 3, 4
SCORPION_VX_PIPE_LOAD_USE_STALL	Scorpion VX pipe load use stall	1, 2, 3, 4
SCORPION_VS_PIPE_WAR_STALL_CYCLES	Scorpion VS pipe WAR stall cycles	1, 2, 3, 4
SCORPION_VS_PIPE_WAW_STALL_CYCLES	Scorpion VS pipe WAW stall cycles	1, 2, 3, 4
SCORPION_VS_PIPE_RAW_STALL_CYCLES	Scorpion VS pipe RAW stall cycles	1, 2, 3, 4
SCORPION_EXCEPTIONS_INV_OPERATION	Scorpion invalid operation exceptions	1, 2, 3, 4
SCORPION_EXCEPTIONS_DIV_BY_ZERO	Scorpion divide by zero exceptions	1, 2, 3, 4
SCORPION_COND_INST_FAIL_VX_PIPE	Scorpion conditional instruction fail VX pipe	1, 2, 3, 4
SCORPION_COND_INST_FAIL_VS_PIPE	Scorpion conditional instruction fail VS pipe	1, 2, 3, 4
SCORPION_EXCEPTIONS_OVERFLOW	Scorpion overflow exceptions	1, 2, 3, 4
SCORPION_EXCEPTIONS_UNDERFLOW	Scorpion underflow exceptions	1, 2, 3, 4
SCORPION_EXCEPTIONS_DENORM	Scorpion denorm exceptions	1, 2, 3, 4
BANK_AB_HIT	L2 hit rates bank A/B hits	1, 2, 3, 4
BANK_AB_ACCESS	L2 hit rates bank A/B accesses	1, 2, 3, 4
BANK_CD_HIT	L2 hit rates bank C/D hits	1, 2, 3, 4
BANK_CD_ACCESS	L2 hit rates bank C/D accesses	1, 2, 3, 4
BANK_AB_DSIDE_HIT	L2 hit rates bank A/B d-side hits	1, 2, 3, 4
BANK_AB_DSIDE_ACCESS	L2 hit rates bank A/B d-side accesses	1, 2, 3, 4
BANK_CD_DSIDE_HIT	L2 hit rates bank C/D d-side hits	1, 2, 3, 4
BANK_CD_DSIDE_ACCESS	L2 hit rates bank C/D d-side accesses	1, 2, 3, 4
BANK_AB_ISIDE_HIT	L2 hit rates bank A/B i-side hits	1, 2, 3, 4
BANK_AB_ISIDE_ACCESS	L2 hit rates bank A/B i-side accesses	1, 2, 3, 4
BANK_CD_ISIDE_HIT	L2 hit rates bank C/D i-side hits	1, 2, 3, 4
BANK_CD_ISIDE_ACCESS	L2 hit rates bank C/D i-side accesses	1, 2, 3, 4
ISIDE_RD_WAIT	fills and castouts cycles that i-side RD requests wait on data from bus	1, 2, 3, 4
DSIDE_RD_WAIT	fills and castouts cycles that d-side RD requests wait on data from bus	1, 2, 3, 4
BANK_BYPASS_WRITE	fills and castouts bank bypass writes	1, 2, 3, 4
BANK_AB_NON_CASTOUT	fills and castouts bank A/B non-castout writes to bus	1, 2, 3, 4
BANK_AB_L2_CASTOUT	fills and castouts bank A/B L2 castouts (granules)	1, 2, 3, 4
BANK_CD_NON_CASTOUT	fills and castouts bank C/D non-castout writes to bus	1, 2, 3, 4
BANK_CD_L2_CASTOUT	fills and castouts bank C/D L2 castouts (granules)	1, 2, 3, 4