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ARM V7 ScorpionMP events

This is a list of all ARM V7 ScorpionMP's performance counter event types. Please see ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition Scorpion Processor Family Programmer's Reference Manual (PRM)

NameDescriptionCounters usableUnit mask options
SW_INCR Software increment of PMNC registers 1, 2, 3, 4, 5, 6
L1I_CACHE_REFILL Level 1 instruction cache refill 1, 2, 3, 4, 5, 6
L1I_TLB_REFILL Level 1 instruction TLB refill 1, 2, 3, 4, 5, 6
L1D_CACHE_REFILL Level 1 data cache refill 1, 2, 3, 4, 5, 6
L1D_CACHE Level 1 data cache access 1, 2, 3, 4, 5, 6
L1D_TLB_REFILL Level 1 data TLB refill 1, 2, 3, 4, 5, 6
LD_RETIRED Load instruction architecturally executed, condition code pass 1, 2, 3, 4, 5, 6
ST_RETIRED Store instruction architecturally executed, condition code pass 1, 2, 3, 4, 5, 6
INST_RETIRED Instruction architecturally executed 1, 2, 3, 4, 5, 6
EXC_TAKEN Exception taken 1, 2, 3, 4, 5, 6
EXC_RETURN Exception return instruction architecturally executed 1, 2, 3, 4, 5, 6
CID_WRITE_RETIRED Write to CONTEXTIDR register architecturally executed 1, 2, 3, 4, 5, 6
PC_WRITE_RETIRED Software change of the PC architecturally executed, condition code pass 1, 2, 3, 4, 5, 6
BR_IMMED_RETIRED Immediate branch instruction architecturally executed 1, 2, 3, 4, 5, 6
BR_RETURN_RETIRED Procedure return instruction architecturally executed, condition code pass 1, 2, 3, 4, 5, 6
UNALIGNED_LDST_RETIRED Unaligned load or store instruction architecturally executed, condition code pass 1, 2, 3, 4, 5, 6
BR_MIS_PRED Mispredicted or not predicted branch speculatively executed 1, 2, 3, 4, 5, 6
BR_PRED Predictable branch speculatively executed 1, 2, 3, 4, 5, 6
MEM_ACCESS Data memory access 1, 2, 3, 4, 5, 6
L1I_CACHE Level 1 instruction cache access 1, 2, 3, 4, 5, 6
L1D_CACHE_WB Level 1 data cache write-back 1, 2, 3, 4, 5, 6
L2D_CACHE Level 2 data cache access 1, 2, 3, 4, 5, 6
L2D_CACHE_REFILL Level 2 data cache refill 1, 2, 3, 4, 5, 6
L2D_CACHE_WB Level 2 data cache write-back 1, 2, 3, 4, 5, 6
BUS_ACCESS Bus access 1, 2, 3, 4, 5, 6
MEMORY_ERROR Local memory error 1, 2, 3, 4, 5, 6
INST_SPEC Instruction speculatively executed 1, 2, 3, 4, 5, 6
TTBR_WRITE_RETIRED Write to TTBR architecturally executed, condition code pass 1, 2, 3, 4, 5, 6
BUS_CYCLES Bus cycle 1, 2, 3, 4, 5, 6
CPU_CYCLES CPU cycle 0
ICACHE_EXPL_INV I-cache explicit invalidates 1, 2, 3, 4
ICACHE_MISS I-cache misses 1, 2, 3, 4
ICACHE_ACCESS I-cache accesses 1, 2, 3, 4
ICACHE_CACHEREQ_L2 I-cache cacheable requests to L2 1, 2, 3, 4
ICACHE_NOCACHE_L2 I-cache non-cacheable requests to L2 1, 2, 3, 4
HIQUP_NOPED Conditional instructions HIQUPs NOPed 1, 2, 3, 4
DATA_ABORT Interrupts and Exceptions Data Abort 1, 2, 3, 4
IRQ Interrupts and Exceptions IRQ 1, 2, 3, 4
FIQ Interrupts and Exceptions FIQ 1, 2, 3, 4
ALL_EXCPT Interrupts and Exceptions All interrupts 1, 2, 3, 4
UNDEF Interrupts and Exceptions Undefined 1, 2, 3, 4
SVC Interrupts and Exceptions SVC 1, 2, 3, 4
SMC Interrupts and Exceptions SMC 1, 2, 3, 4
PREFETCH_ABORT Interrupts and Exceptions Prefetch Abort 1, 2, 3, 4
INDEX_CHECK Interrupts and Exceptions Index Check 1, 2, 3, 4
NULL_CHECK Interrupts and Exceptions Null Check 1, 2, 3, 4
EXPL_ICIALLU I-cache and BTAC Invalidates Explicit ICIALLU 1, 2, 3, 4
IMPL_ICIALLU I-cache and BTAC Invalidates Implicit ICIALLU 1, 2, 3, 4
NONICIALLU_BTAC_INV I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate 1, 2, 3, 4
ICIMVAU_IMPL_ICIALLU I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU 1, 2, 3, 4
SPIPE_ONLY_CYCLES Issue S-pipe only issue cycles 1, 2, 3, 4
XPIPE_ONLY_CYCLES Issue X-pipe only issue cycles 1, 2, 3, 4
DUAL_CYCLES Issue dual issue cycles 1, 2, 3, 4
DISPATCH_ANY_CYCLES Dispatch any dispatch cycles 1, 2, 3, 4
FIFO_FULLBLK_CMT Commits Trace FIFO full Blk CMT 1, 2, 3, 4
FAIL_COND_INST Conditional instructions failing conditional instrs (excluding branches) 1, 2, 3, 4
PASS_COND_INST Conditional instructions passing conditional instrs (excluding branches) 1, 2, 3, 4
ALLOW_VU_CLK Unit Clock Gating Allow VU Clks 1, 2, 3, 4
VU_IDLE Unit Clock Gating VU Idle 1, 2, 3, 4
ALLOW_L2_CLK Unit Clock Gating Allow L2 Clks 1, 2, 3, 4
L2_IDLE Unit Clock Gating L2 Idle 1, 2, 3, 4
DTLB_IMPL_INV_SCTLR_DACR DTLB implicit invalidates writes to SCTLR and DACR 1, 2, 3, 4
DTLB_EXPL_INV DTLB explicit invalidates 1, 2, 3, 4
DTLB_MISS DTLB misses 1, 2, 3, 4
DTLB_ACCESS DTLB accesses 1, 2, 3, 4
SCORPION_ITLB_MISS ITLB misses 1, 2, 3, 4
ITLB_IMPL_INV ITLB implicit ITLB invalidates 1, 2, 3, 4
ITLB_EXPL_INV ITLB explicit ITLB invalidates 1, 2, 3, 4
UTLB_D_MISS UTLB d-side misses 1, 2, 3, 4
UTLB_D_ACCESS UTLB d-side accesses 1, 2, 3, 4
UTLB_I_MISS UTLB i-side misses 1, 2, 3, 4
UTLB_I_ACCESS UTLB i-side accesses 1, 2, 3, 4
UTLB_INV_ASID UTLB invalidate by ASID 1, 2, 3, 4
UTLB_INV_MVA UTLB invalidate by MVA 1, 2, 3, 4
UTLB_INV_ALL UTLB invalidate all 1, 2, 3, 4
S2_HOLD_RDQ_UNAVAIL S2 hold RDQ unavail 1, 2, 3, 4
S2_HOLD S2 hold S2 hold 1, 2, 3, 4
S2_HOLD_DEV_OP S2 hold device op 1, 2, 3, 4
S2_HOLD_ORDER S2 hold strongly ordered op 1, 2, 3, 4
S2_HOLD_BARRIER S2 hold barrier 1, 2, 3, 4
SCORPION_VIU_DUAL_CYCLE Scorpion VIU dual cycle 1, 2, 3, 4
SCORPION_VIU_SINGLE_CYCLE Scorpion VIU single cycle 1, 2, 3, 4
SCORPION_VX_PIPE_WAR_STALL_CYCLES Scorpion VX pipe WAR cycles 1, 2, 3, 4
SCORPION_VX_PIPE_WAW_STALL_CYCLES Scorpion VX pipe WAW cycles 1, 2, 3, 4
SCORPION_VX_PIPE_RAW_STALL_CYCLES Scorpion VX pipe RAW cycles 1, 2, 3, 4
SCORPION_VX_PIPE_LOAD_USE_STALL Scorpion VX pipe load use stall 1, 2, 3, 4
SCORPION_VS_PIPE_WAR_STALL_CYCLES Scorpion VS pipe WAR stall cycles 1, 2, 3, 4
SCORPION_VS_PIPE_WAW_STALL_CYCLES Scorpion VS pipe WAW stall cycles 1, 2, 3, 4
SCORPION_VS_PIPE_RAW_STALL_CYCLES Scorpion VS pipe RAW stall cycles 1, 2, 3, 4
SCORPION_EXCEPTIONS_INV_OPERATION Scorpion invalid operation exceptions 1, 2, 3, 4
SCORPION_EXCEPTIONS_DIV_BY_ZERO Scorpion divide by zero exceptions 1, 2, 3, 4
SCORPION_COND_INST_FAIL_VX_PIPE Scorpion conditional instruction fail VX pipe 1, 2, 3, 4
SCORPION_COND_INST_FAIL_VS_PIPE Scorpion conditional instruction fail VS pipe 1, 2, 3, 4
SCORPION_EXCEPTIONS_OVERFLOW Scorpion overflow exceptions 1, 2, 3, 4
SCORPION_EXCEPTIONS_UNDERFLOW Scorpion underflow exceptions 1, 2, 3, 4
SCORPION_EXCEPTIONS_DENORM Scorpion denorm exceptions 1, 2, 3, 4
SCORPIONMP_NUM_BARRIERS Barriers 1, 2, 3, 4
SCORPIONMP_BARRIER_CYCLES Barrier cycles 1, 2, 3, 4
Rules of Optimization: Rule 1: Don't do it. Rule 2 (for experts only): Don't do it yet. - M.A. Jackson
2014/09/12