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APM X-Gene events

This is a list of all APM X-Gene's performance counter event types. Please see ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile DDI (ARM DDI0487A.a).

NameDescriptionCounters usableUnit mask options
SW_INCR Instruction architecturally executed, condition code check pass, software increment all
L1I_CACHE_REFILL Level 1 instruction cache refill all
L1I_TLB_REFILL Level 1 instruction TLB refill all
L1D_CACHE_REFILL Level 1 data cache refill all
L1D_CACHE Level 1 data cache access all
L1D_TLB_REFILL Level 1 data TLB refill all
LD_RETIRED Instruction architecturally executed, condition code check pass, load all
ST_RETIRED Instruction architecturally executed, condition code check pass, store all
INST_RETIRED Instruction architecturally executed all
EXC_TAKEN Exception taken all
EXC_RETURN Instruction architecturally executed, condition code check pass, exception return all
CID_WRITE_RETIRED Instruction architecturally executed, condition code check pass, write to CONTEXTIDR all
PC_WRITE_RETIRED Instruction architecturally executed, condition code check pass, software change of the PC all
BR_IMMED_RETIRED Instruction architecturally executed, immediate branch all
BR_RETURN_RETIRED Instruction architecturally executed, condition code check pass, procedure return all
UNALIGNED_LDST_RETIRED Instruction architecturally executed, condition code check pass, unaligned load or store all
BR_MIS_PRED Mispredicted or not predicted branch speculatively executed all
CPU_CYCLES Cycle all
BR_PRED Predictable branch speculatively executed all
MEM_ACCESS Data memory access all
L1I_CACHE Level 1 instruction cache access all
L1D_CACHE_WB Level 1 data cache write-back all
L2D_CACHE Level 2 data cache access all
L2D_CACHE_REFILL Level 2 data cache refill all
L2D_CACHE_WB Level 2 data cache write-back all
BUS_ACCESS Bus access all
MEMORY_ERROR Local memory error all
INST_SPEC Operation speculatively executed all
TTBR_WRITE_RETIRED Instruction architecturally executed, condition code check pass, write to TTBR all
BUS_CYCLES Bus cycle all
L1D_CACHE_ALLOCATE Level 1 data cache allocation without refill all
L2D_CACHE_ALLOCATE Level 2 data cache allocation without refill all
Measurement is a crucial component of performance improvement since reasoning and intuition are fallible guides and must be supplemented with tools like timing commands and profilers. - The Practice of Programming, Brian W. Kernighan and Rob Pike
2014/09/12