This is a list of all AVR32's performance counter event types. See AVR32 Architecture Manual, Chapter 6: Performance Counters.
| Name | Description | Counters usable | Unit mask options |
| IFU_IFETCH_MISS | number of instruction fetch misses | 1, 2 | |
| CYCLES_IFU_MEM_STALL | cycles instruction fetch pipe is stalled | 1, 2 | |
| CYCLES_DATA_STALL | cycles stall due to data dependency | 1, 2 | |
| ITLB_MISS | number of Instruction TLB misses | 1, 2 | |
| DTLB_MISS | number of Data TLB misses | 1, 2 | |
| BR_INST_EXECUTED | branch instruction executed w/ or w/o program flow change | 1, 2 | |
| BR_INST_MISS_PRED | branch mispredicted | 1, 2 | |
| INSN_EXECUTED | instructions executed | 1, 2 | |
| DCACHE_WBUF_FULL | data cache write buffers full | 1, 2 | |
| CYCLES_DCACHE_WBUF_FULL | cycles stalled due to data cache write buffers full | 1, 2 | |
| DCACHE_READ_MISS | data cache read miss | 1, 2 | |
| CYCLES_DCACHE_READ_MISS | cycles stalled due to data cache read miss | 1, 2 | |
| WRITE_ACCESS | write access | 1, 2 | |
| CYCLES_WRITE_ACCESS | cycles when write access is ongoing | 1, 2 | |
| READ_ACCESS | read access | 1, 2 | |
| CYCLES_READ_ACCESS | cycles when read access is ongoing | 1, 2 | |
| CACHE_STALL | read or write access that stalled | 1, 2 | |
| CYCLES_CACHE_STALL | cycles stalled doing read or write access | 1, 2 | |
| DCACHE_ACCESS | data cache access | 1, 2 | |
| CYCLES_DCACHE_ACCESS | cycles when data cache access is ongoing | 1, 2 | |
| DCACHE_WB | data cache line writeback | 1, 2 | |
| ACCUMULATOR_HIT | accumulator cache hit | 1, 2 | |
| ACCUMULATOR_MISS | accumulator cache miss | 1, 2 | |
| BTB_HIT | branch target buffer hit | 1, 2 | |
| CPU_CYCLES | clock cycles counter | 0 |
Don't speculate - benchmark.- Dan Bernstein