First generation Intel Atom events

This is a list of all Intel Atom's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A.

Name	Description	Counters usable	Unit mask options
CPU_CLK_UNHALTED	Clock cycles when not halted	all	0x00: core_p Core cycles when core is not halted 0x01: bus Bus cycles when core is not halted 0x02: no_other Bus cycles when core is active and the other is halted
UNHALTED_REFERENCE_CYCLES	Unhalted reference cycles	all	0x01: No unit mask
INST_RETIRED	number of instructions retired	all	0x01: No unit mask
LLC_MISSES	Last level cache demand requests from this core that missed the LLC	all	0x41: No unit mask
LLC_REFS	Last level cache demand requests from this core	all	0x4f: No unit mask
BR_INST_RETIRED	number of branch instructions retired	all	0x00: any Retired branch instructions 0x01: pred_not_taken Retired branch instructions that were predicted not-taken 0x02: mispred_not_taken Retired branch instructions that were mispredicted not-taken 0x04: pred_taken Retired branch instructions that were predicted taken 0x08: mispred_taken Retired branch instructions that were mispredicted taken 0x0a: mispred Retired mispredicted branch instructions (precise event) 0x0c: taken Retired taken branch instructions 0x0f: any1 Retired branch instructions
BR_MISS_PRED_RETIRED	number of mispredicted branches retired (precise)	all
STORE_FORWARDS	Good store forwards	all	0x81: good Good store forwards
SEGMENT_REG_LOADS	Number of segment register loads	all	0x00: any Number of segment register loads
PREFETCH	Streaming SIMD Extensions (SSE) Prefetch instructions executed	all	0x01: prefetcht0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed 0x06: sw_l2 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed 0x08: prefetchnta Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
DATA_TLB_MISSES	Memory accesses that missed the DTLB	all	0x07: dtlb_miss Memory accesses that missed the DTLB 0x05: dtlb_miss_ld DTLB misses due to load operations 0x09: l0_dtlb_miss_ld L0_DTLB misses due to load operations 0x06: dtlb_miss_st DTLB misses due to store operations
PAGE_WALKS	Page walks	all	0x03: walks Number of page-walks executed 0x03: cycles Duration of page-walks in core cycles
X87_COMP_OPS_EXE	Floating point computational micro-ops	all	0x01: s Floating point computational micro-ops executed 0x81: ar Floating point computational micro-ops retired
FP_ASSIST	Floating point assists	all	0x81: ar Floating point assists
MUL	Multiply operations	all	0x01: s Multiply operations executed 0x81: ar Multiply operations retired
DIV	Divide operations	all	0x01: s Divide operations executed 0x81: ar Divide operations retired
CYCLES_DIV_BUSY	Cycles the driver is busy	all	0x01: No unit mask
CORE	Cycles L2 address bus is in use	all	0x180: all All cores. 0x80: this This Core.
L2_DBUS_BUSY	Cycles the L2 cache data bus is busy	all	0x180: all All cores. 0x80: this This Core.
L2_LINES_IN	L2 cache misses	all	0x180: all All cores. 0x80: this This Core. 0x60: all All inclusive 0x20: hw Hardware prefetch only 0x00: exclude_hw Exclude hardware prefetch
L2_M_LINES_IN	L2 cache line modifications	all	0x180: all All cores. 0x80: this This Core.
L2_LINES_OUT	L2 cache lines evicted	all	0x180: all All cores. 0x80: this This Core. 0x60: all All inclusive 0x20: hw Hardware prefetch only 0x00: exclude_hw Exclude hardware prefetch
L2_M_LINES_OUT	Modified lines evicted from the L2 cache	all	0x180: all All cores. 0x80: this This Core. 0x60: all All inclusive 0x20: hw Hardware prefetch only 0x00: exclude_hw Exclude hardware prefetch
L2_IFETCH	L2 cacheable instruction fetch requests	all	0x180: all All cores. 0x80: this This Core. 0x08: modified Counts modified state 0x04: exclusive Counts exclusive state 0x02: shared Counts shared state 0x01: invalid Counts invalid state
L2_LD	L2 cache reads	all	0x180: all All cores. 0x80: this This Core. 0x60: all All inclusive 0x20: hw Hardware prefetch only 0x00: exclude_hw Exclude hardware prefetch 0x08: modified Counts modified state 0x04: exclusive Counts exclusive state 0x02: shared Counts shared state 0x01: invalid Counts invalid state
L2_ST	L2 store requests	all	0x180: all All cores. 0x80: this This Core. 0x08: modified Counts modified state 0x04: exclusive Counts exclusive state 0x02: shared Counts shared state 0x01: invalid Counts invalid state
L2_LOCK	L2 locked accesses	all	0x180: all All cores. 0x80: this This Core. 0x08: modified Counts modified state 0x04: exclusive Counts exclusive state 0x02: shared Counts shared state 0x01: invalid Counts invalid state
L2_RQSTS	L2 cache requests	all	0x41: i_state L2 cache demand requests from this core that missed the L2 0x4f: mesi L2 cache demand requests from this core 0x180: all All cores. 0x80: this This Core. 0x60: all All inclusive 0x20: hw Hardware prefetch only 0x00: exclude_hw Exclude hardware prefetch 0x08: modified Counts modified state 0x04: exclusive Counts exclusive state 0x02: shared Counts shared state 0x01: invalid Counts invalid state
L2_REJECT_BUSQ	Rejected L2 cache requests	all	0x180: all All cores. 0x80: this This Core. 0x60: all All inclusive 0x20: hw Hardware prefetch only 0x00: exclude_hw Exclude hardware prefetch 0x08: modified Counts modified state 0x04: exclusive Counts exclusive state 0x02: shared Counts shared state 0x01: invalid Counts invalid state
L2_NO_REQ	Cycles no L2 cache requests are pending	all	0x180: all All cores. 0x80: this This Core.
EIST_TRANS	Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions	all
THERMAL_TRIP	Number of thermal trips	all	0xc0: thermal_trip Number of thermal trips.
L1D_CACHE	L1d Cache accesses	all	0x21: ld L1 Cacheable Data Reads 0x22: st L1 Cacheable Data Writes
BUS_REQUEST_OUTSTANDING	Outstanding cacheable data read bus requests duration	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_BNR_DRV	Number of Bus Not Ready signals asserted	all	0x00: this This agent 0x40: any Include any agents
BUS_DRDY_CLOCKS	Bus cycles when data is sent on the bus	all	0x00: this This agent 0x40: any Include any agents
BUS_LOCK_CLOCKS	Bus cycles when a LOCK signal is asserted.	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_DATA_RCV	Bus cycles while processor receives data	all	0x180: all All cores. 0x80: this This Core.
BUS_TRANS_BRD	Burst read bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_RFO	RFO bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_WB	Explicit writeback bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_IFETCH	Instruction-fetch bus transactions.	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_INVAL	Invalidate bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_PWR	Partial write bus transaction.	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_P	Partial bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_IO	IO bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_DEF	Deferred bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_BURST	Burst (full cache-line) bus transactions.	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_MEM	Memory bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_TRANS_ANY	All bus transactions	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
EXT_SNOOP	External snoops	all	0x180: all All cores. 0x80: this This Core. 0x08: modified Counts modified state 0x04: exclusive Counts exclusive state 0x02: shared Counts shared state 0x01: invalid Counts invalid state
BUS_HIT_DRV	HIT signal asserted	all	0x00: this This agent 0x40: any Include any agents
BUS_HITM_DRV	HITM signal asserted	all	0x00: this This agent 0x40: any Include any agents
BUSQ_EMPTY	Bus queue is empty	all	0x180: all All cores. 0x80: this This Core.
SNOOP_STALL_DRV	Bus stalled for snoops	all	0x180: all All cores. 0x80: this This Core. 0x00: this This agent 0x40: any Include any agents
BUS_IO_WAIT	IO requests waiting in the bus queue	all	0x180: all All cores. 0x80: this This Core.
ICACHE	Instruction cache accesses	all	0x03: accesses Instruction fetches 0x02: misses Icache miss
ITLB	ITLB events	all	0x04: flush ITLB flushes 0x02: misses ITLB misses
MACRO_INSTS	instructions decoded	all	0x02: cisc_decoded CISC macro instructions decoded 0x03: all_decoded All Instructions decoded
SIMD_UOPS_EXEC	SIMD micro-ops executed	all	0x00: s SIMD micro-ops executed (excluding stores) 0x80: ar SIMD micro-ops retired (excluding stores)
SIMD_SAT_UOP_EXEC	SIMD saturated arithmetic micro-ops executed	all	0x00: s SIMD saturated arithmetic micro-ops executed 0x80: ar SIMD saturated arithmetic micro-ops retired
SIMD_UOP_TYPE_EXEC	SIMD packed microops executed	all	0x01: s SIMD packed multiply microops executed 0x81: ar SIMD packed multiply microops retired 0x02: s SIMD packed shift micro-ops executed 0x82: ar SIMD packed shift micro-ops retired 0x04: s SIMD pack micro-ops executed 0x84: ar SIMD pack micro-ops retired 0x08: s SIMD unpack micro-ops executed 0x88: ar SIMD unpack micro-ops retired 0x10: s SIMD packed logical microops executed 0x90: ar SIMD packed logical microops retired 0x20: s SIMD packed arithmetic micro-ops executed 0xa0: ar SIMD packed arithmetic micro-ops retired
UOPS_RETIRED	Micro-ops retired	all	0x10: any Micro-ops retired
MACHINE_CLEARS	Self-Modifying Code detected	all	0x01: No unit mask
CYCLES_INT_MASKED	Cycles during which interrupts are disabled	all	0x01: cycles_int_masked Cycles during which interrupts are disabled 0x02: cycles_int_pending_and_masked Cycles during which interrupts are pending and disabled
SIMD_INST_RETIRED	Retired Streaming SIMD Extensions (SSE) instructions	all	0x01: packed_single Retired Streaming SIMD Extensions (SSE) packed-single instructions 0x02: scalar_single Retired Streaming SIMD Extensions (SSE) scalar-single instructions 0x04: packed_double Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions 0x08: scalar_double Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions 0x10: vector Retired Streaming SIMD Extensions 2 (SSE2) vector instructions 0x1f: any Retired Streaming SIMD instructions
HW_INT_RCV	Hardware interrupts received	all
SIMD_COMP_INST_RETIRED	Retired computational Streaming SIMD Extensions (SSE) instructions.	all	0x01: packed_single Retired computational Streaming SIMD Extensions (SSE) packed-single instructions 0x02: scalar_single Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions 0x04: packed_double Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions 0x08: scalar_double Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions
MEM_LOAD_RETIRED	Retired loads	all	0x01: l2_hit Retired loads that hit the L2 cache (precise event) 0x02: l2_miss Retired loads that miss the L2 cache (precise event) 0x04: dtlb_miss Retired loads that miss the DTLB (precise event)
SIMD_ASSIST	SIMD assists invoked	all
SIMD_INSTR_RETIRED	SIMD Instructions retired	all
SIMD_SAT_INSTR_RETIRED	Saturated arithmetic instructions retired	all
BR_INST_DECODED	Branch instructions decoded	all
BOGUS_BR	Bogus branches	all
BACLEARS	BACLEARS asserted	all	0x01: No unit mask