Intel ia64 Itanium2 events

This is a list of ia64 Itanium2 core CPU's performance counter event types. Please see the Intel Architecture Itanium Family Reference Manual Chapter 10.

Name	Description	Counters usable	Unit mask options
CPU_CYCLES	CPU Cycles	all
IA64_INST_RETIRED	IA-64 Instructions Retired	all
IA32_INST_RETIRED	IA-32 Instructions Retired	all
IA32_ISA_TRANSITIONS	Itanium to/from IA-32 ISA Transitions	all
DISP_STALLED	Number of cycles dispersal stalled	all
INST_DISPERSED	Syllables Dispersed from REN to REG stage	all
SYLL_NOT_DISPERSED	Syllables not dispersed	all	0x01: EXPL 0x02: IMPL 0x04: FE 0x08: MLI 0x0f: ALL
SYLL_OVERCOUNT	Syllables overcounted	all	0x01: EXPL 0x02: IMPL 0x03: ALL
ALAT_CAPACITY_MISS	ALAT Entry Replaced	all	0x01: INT 0x02: FP 0x03: ALL
FP_FAILED_FCHKF	Failed fchkf	all
FP_FALSE_SIRSTALL	SIR stall without a trap	all
FP_FLUSH_TO_ZERO	Result Flushed to Zero	all
FP_OPS_RETIRED	Retired FP operations	all
FP_TRUE_SIRSTALL	SIR stall asserted and leads to a trap	all
IA64_TAGGED_INST_RETIRED	Retired Tagged Instructions	all	0x00: IBRP0_PMB8 0x01: IBRP1_PMB9 0x02: IBRP2_PMC8 0x03: IBRP3_PMC9
INST_CHKA_LDC_ALAT	Advanced Check Loads	all	0x01: INT 0x02: FP 0x03: ALL
INST_FAILED_CHKA_LDC_ALAT	Failed Advanced Check Loads	all	0x01: INT 0x02: FP 0x03: ALL
INST_FAILED_CHKS_RETIRED	Failed Speculative Check Loads	all	0x01: INT 0x02: FP 0x03: ALL
NOPS_RETIRED	Retired NOP Instructions	all
PREDICATE_SQUASHED_RETIRED	Instructions Squashed Due to Predicate Off`	all
BACK_END_BUBBLE	Full pipe bubbles in main pipe	all	0x00: ALL 0x01: FE 0x02: L1D_FPU_RSE
BE_EXE_BUBBLE	Full pipe bubbles in main pipe due to Execution unit stalls	all	0x00: ALL 0x01: GRALL 0x02: FRALL 0x03: PR 0x04: ARCR 0x05: GRCR 0x06: CANCEL 0x07: BANK_SWITCH 0x08: ARCR_PR_CANCEL_BANK
BE_FLUSH_BUBBLE	Full pipe bubbles in main pipe due to flushes	all	0x00: ALL 0x01: BRU 0x02: XPN
BE_L1D_FPU_BUBBLE	Full pipe bubbles in main pipe due to FP or L1 dcache	all	0x00: ALL 0x01: FPU 0x02: L1D 0x03: L1D_FULLSTBUF 0x04: L1D_DCURECIR 0x05: L1D_HPW 0x07: L1D_FILLCONF 0x08: L1D_DCS 0x09: L1D_L2BPRESS 0x0a: L1D_TLB 0x0b: L1D_LDCONF 0x0c: L1D_LDCHK 0x0d: L1D_NAT 0x0e: L1D_STBUFRECIR 0x0f: L1D_NATCONF
BE_RSE_BUBBLE	Full pipe bubbles in main pipe due to RSE stalls	all	0x00: ALL 0x01: BANK_SWITCH 0x02: AR_DEP 0x03: OVERFLOW 0x04: UNDERFLOW 0x05: LOADRS
FE_BUBBLE	Bubbles seen by FE	all	0x00: ALL 0x01: FEFLUSH 0x03: GROUP1 0x04: GROUP2 0x05: IBFULL 0x06: IMISS 0x07: TLBMISS 0x08: FILL_RECIRC 0x09: BRANCH 0x0a: GROUP3 0x0b: ALLBUT_FEFLUSH_BUBBLE 0x0c: ALLBUT_IBFULL 0x0d: BUBBLE
FE_LOST_BW	Invalid bundles at the entrance to IB	all	0x00: ALL 0x01: FEFLUSH 0x04: UNREACHED 0x05: IBFULL 0x06: IMISS 0x07: TLBMISS 0x08: FILL_RECIRC 0x09: BI 0x0a: BRQ 0x0b: PLP 0x0c: BR_ILOCK 0x0d: BUBBLE
IDEAL_BE_LOST_BW_DUE_TO_FE	Invalid bundles at the exit from IB	all	0x00: ALL 0x01: FEFLUSH 0x04: UNREACHED 0x05: IBFULL 0x06: IMISS 0x07: TLBMISS 0x08: FILL_RECIRC 0x09: BI 0x0a: BRQ 0x0b: PLP 0x0c: BR_ILOCK 0x0d: BUBBLE
BE_BR_MISPRED_DETAIL	BE branch misprediction detail	all	0x00: ANY 0x01: STG 0x02: ROT 0x03: PFS
BRANCH_EVENT	Branch Event Captured	all
BR_MISPRED_DETAIL	Branch Mispredict Detail	all	0x00: ALL.ALL_PRED 0x01: ALL.CORRECT_PRED 0x02: ALL.WRONG_PATH 0x03: ALL.WRONG_TARGET 0x04: IPREL.ALL_PRED 0x05: IPREL.CORRECT_PRED 0x06: IPREL.WRONG_PATH 0x07: IPREL.WRONG_TARGET 0x08: RETURN.ALL_PRED 0x09: RETURN.CORRECT_PRED 0x0a: RETURN.WRONG_PATH 0x0b: RETURN.WRONG_TARGET 0x0c: NRETIND.ALL_PRED 0x0d: NRETIND.CORRECT_PRED 0x0e: NRETIND.WRONG_PATH 0x0f: NRETIND.WRONG_TARGET
BR_MISPRED_DETAIL2	FE Branch Mispredict Detail (Unknown path component)	all	0x00: ALL.ALL_UNKNOWN_PRED 0x01: ALL.UKNOWN_PATH_CORRECT_PRED 0x02: ALL.UKNOWN_PATH_WRONG_PATH 0x04: IPREL.ALL_UNKNOWN_PRED 0x05: IPREL.UNKNOWN_PATH_CORRECT_PRED 0x06: IPREL.UNKNOWN_PATH_WRONG_PATH 0x08: RETURN.ALL_UNKNOWN_PRED 0x09: RETURN.UNKNOWN_PATH_CORRECT_PRED 0x0a: RETURN.UNKNOWN_PATH_WRONG_PATH 0x0c: NRETIND.ALL_UNKNOWN_PRED 0x0d: NRETIND.UNKNOWN_PATH_CORRECT_PRED 0x0e: NRETIND.UNKNOWN_PATH_WRONG_PATH
BR_PATH_PRED	FE Branch Path Prediction Detail	all	0x00: ALL.MISPRED_NOTTAKEN 0x01: ALL.MISPRED_TAKEN 0x02: ALL.OKPRED_NOTTAKEN 0x03: ALL.OKPRED_TAKEN 0x04: IPREL.MISPRED_NOTTAKEN 0x05: IPREL.MISPRED_TAKEN 0x06: IPREL.OKPRED_NOTTAKEN 0x07: IPREL.OKPRED_TAKEN 0x08: RETURN.MISPRED_NOTTAKEN 0x09: RETURN.MISPRED_TAKEN 0x0a: RETURN.OKPRED_NOTTAKEN 0x0b: RETURN.OKPRED_TAKEN 0x0c: NRETIND.MISPRED_NOTTAKEN 0x0d: NRETIND.MISPRED_TAKEN 0x0e: NRETIND.OKPRED_NOTTAKEN 0x0f: NRETIND.OKPRED_TAKEN
BR_PATH_PRED2	FE Branch Path Prediction Detail (Unknown prediction component)	all	0x00: ALL.UNKNOWNPRED_NOTTAKEN 0x01: ALL.UNKNOWNPRED_TAKEN 0x04: IPREL.UNKNOWNPRED_NOTTAKEN 0x05: IPREL.UNKNOWNPRED__TAKEN 0x08: RETURN.UNKNOWNPRED_NOTTAKEN 0x09: RETURN.UNKNOWNPRED_TAKEN 0x0c: NRETIND.UNKNOWNPRED_NOTTAKEN 0x0d: NRETIND.UNKNOWNPRED_TAKEN
ENCBR_MISPRED_DETAIL	Number of encoded branches retired	all	0x00: ALL.ALL_PRED 0x01: ALL.CORRECT_PRED 0x02: ALL.WRONG_PATH 0x03: ALL.WRONG_TARGET 0x08: OVERSUB.ALL_PRED 0x09: OVERSUB.CORRECT_PRED 0x0a: OVERSUB.CORRECT_PRED 0x0b: OVERSUB.WRONGPATH 0x0c: ALL2.ALL_PRED 0x0d: ALL2.CORRECT_PRED 0x0e: ALL2.WRONG_PATH 0x0f: ALL2.WRONG_TARGET
ISB_BUNPAIRS_IN	Bundle pairs written from L2 into FE	all
L1I_EAR_EVENTS	Instruction EAR Events	all
L1I_FETCH_ISB_HIT	"\"Just-in-time\" instruction fetch hitting in and being bypassed from ISB	all
L1I_FETCH_RAB_HIT	Instruction fetch hitting in RAB	all
L1I_FILLS	L1 Instruction Cache Fills	all
L1I_PREFETCHES	Instruction Prefetch Requests	all
L2_INST_DEMAND_READS	L1 Instruction Cache and ISB Misses	all
L1I_PREFETCH_STALL	Why prefetch pipeline is stalled?	all	0x02: FLOW 0x03: ALL
L1I_PURGE	L1ITLB purges handled by L1I	all
L1I_PVAB_OVERFLOW	PVAB overflow	all
L1I_RAB_ALMOST_FULL	Is RAB almost full?	all
L1I_RAB_FULL	Is RAB full?	all
L1I_READS	L1 Instruction Cache Read	all
L1I_SNOOP	Snoop requests handled by L1I	all
L1I_STRM_PREFETCHES	L1 Instruction Cache line prefetch requests	all
L2_INST_PREFETCHES	Instruction Prefetch Requests	all
DATA_EAR_EVENTS	Data Cache EAR Events	all
L1DTLB_TRANSFER	L1DTLB misses that hit in the L2DTLB for accesses counted in L1D_READS	1
L2DTLB_MISSES	L2DTLB Misses	1
L1D_READS_SET0	L1 Data Cache Reads	1
DATA_REFERENCES_SET0	Data memory references issued to memory pipeline	1
L1D_READS_SET1	L1 Data Cache Reads	1
DATA_REFERENCES_SET1	Data memory references issued to memory pipeline	1
L1D_READ_MISSES	L1 Data Cache Read Misses	1	0x00: ALL 0x01: RSE_FILL
BE_L1D_FPU_BUBBLE	Full pipe bubbles in main pipe due to FP or L1 dcache	1	0x00: ALL 0x01: FPU 0x02: L1D 0x03: L1D_FULLSTBUF 0x04: L1D_DCURECIR 0x05: L1D_HPW 0x07: L1D_FILLCONF 0x08: L1D_DCS 0x09: L1D_L2BPRESS 0x0a: L1D_TLB 0x0b: L1D_LDCONF 0x0c: L1D_LDCHK 0x0d: L1D_NAT 0x0e: L1D_STBUFRECIR 0x0f: L1D_NATCONF
LOADS_RETIRED	Retired Loads	1
MISALIGNED_LOADS_RETIRED	Retired Misaligned Load Instructions	1
UC_LOADS_RETIRED	Retired Uncacheable Loads	1
STORES_RETIRED	Retired Stores	1
MISALIGNED_STORES_RETIRED	Retired Misaligned Store Instructions	1
UC_STORES_RETIRED	Retired Uncacheable Stores	1
L2_FILLB_FULL	L2D Fill buffer is full	all
L2_GOT_RECIRC_IFETCH	Instruction fetch recirculates received by L2D	all	0x08: default:0x0} } };
L2_ISSUED_RECIRC_IFETCH	Instruction fetch recirculates issued by L2D	all	0x08: default:0x0} } };
L2_MISSES	L2 Misses	all
L2_OPS_ISSUED	Different operations issued by L2D	all	0x08: INT_LOAD 0x09: FP_LOAD 0x0a: RMW 0x0b: STORE 0x0c: NST_NLD
L2_IFET_CANCELS	Instruction fetch cancels by the L2.	0	0x00: ANY 0x02: BYPASS 0x04: DIDNT_RECIR 0x05: RECIRC_OVER_SUB 0x06: ST_FILL_WB 0x07: DATA_RD 0x08: PREEMPT 0x0c: CHG_PRIO 0x0d: IFETCH_BYP
L2_IFET_CANCELS	Instruction fetch cancels by the L2.	0	0x00: ANY 0x02: BYPASS 0x04: DIDNT_RECIR 0x05: RECIRC_OVER_SUB 0x06: ST_FILL_WB 0x07: DATA_RD 0x08: PREEMPT 0x0c: CHG_PRIO 0x0d: IFETCH_BYP
L2_IFET_CANCELS	Instruction fetch cancels by the L2.	0	0x00: ANY 0x02: BYPASS 0x04: DIDNT_RECIR 0x05: RECIRC_OVER_SUB 0x06: ST_FILL_WB 0x07: DATA_RD 0x08: PREEMPT 0x0c: CHG_PRIO 0x0d: IFETCH_BYP
L2_IFET_CANCELS	Instruction fetch cancels by the L2.	0	0x00: ANY 0x02: BYPASS 0x04: DIDNT_RECIR 0x05: RECIRC_OVER_SUB 0x06: ST_FILL_WB 0x07: DATA_RD 0x08: PREEMPT 0x0c: CHG_PRIO 0x0d: IFETCH_BYP
L2_OZQ_ACQUIRE	Clocks with acquire ordering attribute existed in L2 OZQ	0
L2_OZQ_ACQUIRE	Clocks with acquire ordering attribute existed in L2 OZQ	0
L2_OZQ_ACQUIRE	Clocks with acquire ordering attribute existed in L2 OZQ	0
L2_OZQ_ACQUIRE	Clocks with acquire ordering attribute existed in L2 OZQ	0
L2_OZQ_CANCELS0	L2 OZQ cancels	0	0x00: ANY 0x01: LATE_SPEC_BYP 0x02: LATE_RELEASE 0x03: LATE_ACQUIRE 0x04: LATE_BYP_EFFRELEASE
L2_OZQ_CANCELS1	L2 OZQ cancels	0	0x00: REL 0x01: BANK_CONF 0x02: L2D_ST_MAT 0x04: SYNC 0x05: HPW_IFETCH_CONF 0x06: CANC_L2M_ST 0x07: L1_FILL_CONF 0x08: ST_FILL_CONF 0x09: CCV 0x0a: SEM 0x0b: L2M_ST_MAT 0x0c: MFA 0x0d: L2A_ST_MAT 0x0e: L1DF_L2M 0x0f: ECC
L2_OZQ_CANCELS2	L2 OZQ cancels	0	0x00: RECIRC_OVER_SUB 0x01: CANC_L2C_ST 0x02: L2C_ST_MAT 0x03: SCRUB 0x04: ACQ 0x05: READ_WB_CONF 0x06: OZ_DATA_CONF 0x08: L2FILL_ST_CONF 0x09: DIDNT_RECIRC 0x0a: WEIRD 0x0c: OVER_SUB 0x0d: CANC_L2D_ST 0x0f: D_IFET
L2_OZQ_RELEASE	Clocks with release ordering attribute existed in L2 OZQ	0
L2_OZQ_RELEASE	Clocks with release ordering attribute existed in L2 OZQ	0
L2_OZQ_RELEASE	Clocks with release ordering attribute existed in L2 OZQ	0
L2_OZQ_RELEASE	Clocks with release ordering attribute existed in L2 OZQ	0
L2_L3ACCESS_CANCEL	Canceled L3 accesses	0	0x01: SPEC_L3_BYP 0x02: FILLD_FULL 0x05: UC_BLOCKED 0x06: INV_L3_BYP 0x08: EBL_REJECT 0x09: ANY 0x0a: DFETCH 0x0b: IFETCH
L2_FORCE_RECIRC	Forced recirculates	0	0x00: ANY 0x01: SMC_HIT 0x02: L1W 0x04: TAG_NOTOK 0x05: TRAN_PREF 0x06: SNP_OR_L3 0x08: VIC_PEND 0x09: FILL_HIT 0x0a: IPF_MISS 0x0b: VIC_BUF_FULL 0x0c: OZQ_MISS 0x0d: SAME_INDEX 0x0e: FRC_RECIRC
L2_BAD_LINES_SELECTED	Valid line replaced when invalid line is available	0
L2_BYPASS	Count bypass	0	0x00: L2_DATA1 0x01: L2_DATA2 0x02: L3_DATA1 0x04: L2_INST1 0x05: L2_INST2 0x06: L3_INST1
L2_STORE_HIT_SHARED	Store hit a shared line	0
L2_GOT_RECIRC_IFETCH	Instruction fetch recirculates received by L2D	0	0x08: default:0x0} } };
L2_ISSUED_RECIRC_IFETCH	Instruction fetch recirculates issued by L2D	0	0x08: default:0x0} } };
L2_OPS_ISSUED	Different operations issued by L2D	0	0x08: INT_LOAD 0x09: FP_LOAD 0x0a: RMW 0x0b: STORE 0x0c: NST_NLD
L2_OZQ_FULL	L2D OZQ is full	0
L2_OZDB_FULL	L2D OZQ is full	0
L2_VICTIMB_FULL	L2D victim buffer is full	0
L2_FILLB_FULL	L2D Fill buffer is full	0
L3_LINES_REPLACED	Cache Lines Replaced	all
L3_MISSES	L3 Misses	all
L3_REFERENCES	L3 References	all
L3_READS	L3 Reads	all	0x01: DINST_FETCH.HIT 0x02: DINST_FETCH.MISS 0x03: DINST_FETCH.ALL 0x05: INST_FETCH.HIT 0x06: INST_FETCH.MISS 0x07: INST_FETCH.ALL 0x09: DATA_READ.HIT 0x0a: DATA_READ.MISS 0x0b: DATA_READ.ALL 0x0d: ALL.HIT 0x0e: ALL.MISS 0x0f: ALL.ALL
L3_WRITES	L3 Writes	all	0x05: DATA_WRITE.HIT 0x06: DATA_WRITE.MISS 0x07: DATA_WRITE.ALL 0x09: L2_WB.HIT 0x0a: L2_WB.MISS 0x0b: L2_WB.ALL 0x0d: ALL.HIT 0x0e: ALL.MISS 0x0f: ALL.ALL
CPU_CPL_CHANGES	Privilege Level Changes	all
DATA_DEBUG_REGISTER_FAULT	Fault due to data debug reg. Match to load/store instruction	all
DATA_DEBUG_REGISTER_MATCHES	Data debug register matches data address of memory reference	all
EXTERN_DP_PINS_0_TO_3	DP pins 0-3 asserted	all	0x01: PIN0 0x02: PIN1 0x04: PIN2 0x08: PIN3 0x0f: ALL
EXTERN_DP_PINS_4_TO_5	DP pins 4-5 asserted	all	0x01: PIN4 0x02: PIN5 0x0f: ALL
SERIALIZATION_EVENTS	Number of srlz.I instructions	all
DTLB_INSERTS_HPW	Hardware Page Walker Installs to DTLB"	all
DTLB_INSERTS_HPW_RETIRED	VHPT entries inserted into DTLB by HW PW	all
HPW_DATA_REFERENCES	Data memory references to VHPT	all
L1ITLB_INSERTS_HPW	L1ITLB Hardware Page Walker Inserts	all
ITLB_MISSES_FETCH	ITLB Misses Demand Fetch	all	0x01: L1ITLB 0x02: L2ITLB 0x03: ALL
BUS_ALL	Bus Transactions	all	0x01: IO 0x02: SELF 0x03: ANY
BUS_BRQ_LIVE_REQ_HI	BRQ Live Requests (two most-significant-bit of the 5-bit outstanding BRQ request count)	all
BUS_BRQ_LIVE_REQ_LO	BRQ Live Requests (three least-significant-bit of the 5-bit outstanding BRQ request count	all
BUS_BRQ_REQ_INSERTED	BRQ Requests Inserted	all
BUS_DATA_CYCLE	Valid data cycle on the Bus	all
BUS_HITM	Bus Hit Modified Line Transactions	all
BUS_IO	IA-32 Compatible IO Bus Transactions	all	0x01: IO 0x02: SELF 0x03: ANY
BUS_IOQ_LIVE_REQ_HI	Inorder Bus Queue Requests (two most-significant-bit of the 4-bit outstanding IOQ request count)	all
BUS_IOQ_LIVE_REQ_LO	Inorder Bus Queue Requests (two least-significant-bit of the 4-bit outstanding IOQ request count)	all
BUS_LOCK	IA-32 Compatible Bus Lock Transactions	all	0x02: SELF 0x03: ANY
BUS_BACKSNP_REQ	Bus Back Snoop Requests	all	0x01: 0x0
BUS_MEMORY	Bus Memory Transactions	all	0x05: EQ_128BYTEIO 0x06: EQ_128BYTE_SELF 0x07: EQ_128BYTE_ANY 0x09: LT_128BYTEIO 0x0a: LT_128BYTE_SELF 0x0b: LT_128BYTE_ANY 0x0d: ALL IO 0x0e: ALL SELF 0x0f: ALL ANY
BUS_MEM_READ	Full Cache line D/I memory RD, RD invalidate, and BRIL	all	0x01: BIL IO 0x02: BIL SELF 0x03: BIL ANY 0x05: BRL IO 0x06: BRL SELF 0x07: BRL_ANY 0x09: BRIL IO 0x0a: BRIL SELF 0x0b: BRIL ANY 0x0d: ALL IO 0x0e: ALL SELF 0x0f: ALL ANY
BUS_MEM_READ_OUT_HI	Outstanding memory RD transactions	all
BUS_MEM_READ_OUT_LO	Outstanding memory RD transactions	all
BUS_OOQ_LIVE_REQ_HI	Out-of-order Bus Queue Requests (two most-significant-bit of the 4-bit outstanding OOQ request count)	all
BUS_OOQ_LIVE_REQ_LO	Out-of-order Bus Queue Requests (three least-significant-bit of the 4-bit outstanding OOQ request count)	all
BUS_RD_DATA	Bus Read Data Transactions	all	0x01: IO 0x02: SELF 0x03: ANY
BUS_RD_HIT	Bus Read Hit Clean Non-local Cache Transactions	all
BUS_RD_HITM	Bus Read Hit Modified Non-local Cache Transactions	all
BUS_RD_INVAL_ALL_HITM	Bus BIL or BRIL Transaction Results in HITM	all
BUS_RD_INVAL_HITM	Bus BIL Transaction Results in HITM	all
BUS_RD_IO	IA-32 Compatible IO Read Transactions	all	0x01: IO 0x02: SELF 0x03: ANY
BUS_RD_PRTL	Bus Read Partial Transactions	all	0x01: IO 0x02: SELF 0x03: ANY
BUS_SNOOPQ_REQ	Bus Snoop Queue Requests	all
BUS_SNOOPS	Bus Snoops Total	all	0x01: IO 0x02: SELF 0x03: ANY
BUS_SNOOPS_HITM	Bus Snoops HIT Modified Cache Line	all	0x02: SELF 0x03: ANY
BUS_SNOOP_STALL_CYCLES	Bus Snoop Stall Cycles (from any agent)	all	0x02: SELF 0x03: ANY
BUS_WR_WB	Bus Write Back Transactions	all	0x05: EQ_128BYTE IO 0x06: EQ_128BYTE SELF 0x07: EQ_128BYTE ANY 0x0a: CCASTOUT SELF 0x0b: CCASTOUT ANY 0x0d: ALL IO 0x0e: ALL SELF 0x0f: ALL ANY
MEM_READ_CURRENT	Current Mem Read Transactions On Bus	all	0x01: IO 0x03: ANY
RSE_CURRENT_REGS_2_TO_0	Current RSE registers	all
RSE_CURRENT_REGS_5_TO_3	Current RSE registers	all
RSE_CURRENT_REGS_6	Current RSE registers	all
RSE_DIRTY_REGS_2_TO_0	Dirty RSE registers	all
RSE_DIRTY_REGS_5_TO_3	Dirty RSE registers	all
RSE_DIRTY_REGS_6	Dirty RSE registers	all
RSE_EVENT_RETIRED	Retired RSE operations	all
RSE_REFERENCES_RETIRED	RSE Accesses	all	0x01: LOAD 0x02: STORE 0x03: ALL
TAGGED_L2_DATA_RETURN_POR	Tagged L2 Data Return Ports 0/1	all