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Intel Pentium II

This is a list of Pentium II core CPU's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A.

NameDescriptionCounters usableUnit mask options
CPU_CLK_UNHALTED clocks processor is not halted all
DATA_MEM_REFS all memory references, cachable and non all
DCU_LINES_IN total lines allocated in the DCU all
DCU_M_LINES_IN number of M state lines allocated in DCU all
DCU_M_LINES_OUT number of M lines evicted from the DCU all
DCU_MISS_OUTSTANDING number of cycles while DCU miss outstanding all
IFU_IFETCH number of non/cachable instruction fetches all
IFU_IFETCH_MISS number of instruction fetch misses all
ITLB_MISS number of ITLB misses all
IFU_MEM_STALL cycles instruction fetch pipe is stalled all
ILD_STALL cycles instruction length decoder is stalled all
L2_IFETCH number of L2 instruction fetches all 0x08: (M)odified cache state
0x04: (E)xclusive cache state
0x02: (S)hared cache state
0x01: (I)nvalid cache state
0x0f: All cache states
L2_LD number of L2 data loads all 0x08: (M)odified cache state
0x04: (E)xclusive cache state
0x02: (S)hared cache state
0x01: (I)nvalid cache state
0x0f: All cache states
L2_ST number of L2 data stores all 0x08: (M)odified cache state
0x04: (E)xclusive cache state
0x02: (S)hared cache state
0x01: (I)nvalid cache state
0x0f: All cache states
L2_LINES_IN number of allocated lines in L2 all
L2_LINES_OUT number of recovered lines from L2 all
L2_M_LINES_INM number of modified lines allocated in L2 all
L2_M_LINES_OUTM number of modified lines removed from L2 all
L2_RQSTS number of L2 requests all 0x08: (M)odified cache state
0x04: (E)xclusive cache state
0x02: (S)hared cache state
0x01: (I)nvalid cache state
0x0f: All cache states
L2_ADS number of L2 address strobes all
L2_DBUS_BUSY number of cycles data bus was busy all
L2_DBUS_BUSY_RD cycles data bus was busy in xfer from L2 to CPU all
BUS_DRDY_CLOCKS number of clocks DRDY is asserted all 0x00: self-generated transactions
0x20: any transactions
BUS_LOCK_CLOCKS number of clocks LOCK is asserted all 0x00: self-generated transactions
0x20: any transactions
BUS_REQ_OUTSTANDING number of outstanding bus requests all
BUS_TRAN_BRD number of burst read transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRAN_RFO number of read for ownership transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRANS_WB number of write back transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRAN_IFETCH number of instruction fetch transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRAN_INVAL number of invalidate transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRAN_PWR number of partial write transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRANS_P number of partial transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRANS_IO number of I/O transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRANS_DEF number of deferred transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRAN_BURST number of burst transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRAN_ANY number of all transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_TRAN_MEM number of memory transactions all 0x00: self-generated transactions
0x20: any transactions
BUS_DATA_RCV bus cycles this processor is receiving data all
BUS_BNR_DRV bus cycles this processor is driving BNR pin all
BUS_HIT_DRV bus cycles this processor is driving HIT pin all
BUS_HITM_DRV bus cycles this processor is driving HITM pin all
BUS_SNOOP_STALL cycles during bus snoop stall all
COMP_FLOP_RET number of computational FP operations retired 0
FLOPS number of computational FP operations executed 0
FP_ASSIST number of FP exceptions handled by microcode 1
MUL number of multiplies 1
DIV number of divides 1
CYCLES_DIV_BUSY cycles divider is busy 0
LD_BLOCKS number of store buffer blocks all
SB_DRAINS number of store buffer drain cycles all
MISALIGN_MEM_REF number of misaligned data memory references all
INST_RETIRED number of instructions retired all
UOPS_RETIRED number of UOPs retired all
INST_DECODED number of instructions decoded all
HW_INT_RX number of hardware interrupts received all
CYCLES_INT_MASKED cycles interrupts are disabled all
CYCLES_INT_PENDING_AND_MASKED cycles interrupts are disabled with pending interrupts all
BR_INST_RETIRED number of branch instructions retired all
BR_MISS_PRED_RETIRED number of mispredicted branches retired all
BR_TAKEN_RETIRED number of taken branches retired all
BR_MISS_PRED_TAKEN_RET number of taken mispredictions branches retired all
BR_INST_DECODED number of branch instructions decoded all
BTB_MISSES number of branches that miss the BTB all
BR_BOGUS number of bogus branches all
BACLEARS number of times BACLEAR is asserted all
RESOURCE_STALLS cycles during resource related stalls all
PARTIAL_RAT_STALLS cycles or events for partial stalls all
SEGMENT_REG_LOADS number of segment register loads all
MMX_INSTR_EXEC number of MMX instructions executed all
MMX_SAT_INSTR_EXEC number of MMX saturating instructions executed all
MMX_UOPS_EXEC number of MMX UOPS executed all 0x0f: mandatory
MMX_INSTR_TYPE_EXEC number of MMX packing instructions all 0x01: MMX packed multiplies
0x02: MMX packed shifts
0x04: MMX pack operations
0x08: MMX unpack operations
0x10: MMX packed logical
0x20: MMX packed arithmetic
0x3f: all of the above
FP_MMX_TRANS MMX-floating point transitions all 0x00: MMX->float operations
0x01: float->MMX operations
MMX_ASSIST number of EMMS instructions executed all
MMX_INSTR_RET number of MMX instructions retired all
SEG_RENAME_STALLS number of segment register renaming stalls all 0x01: ES register
0x02: DS register
0x04: FS register
0x08: GS register
0x0f: ES, DS, FS, GS registers
SEG_REG_RENAMES number of segment register renames all 0x01: ES register
0x02: DS register
0x04: FS register
0x08: GS register
0x0f: ES, DS, FS, GS registers
RET_SEG_RENAMES number of segment register rename events retired all
Bottlenecks occur in surprising places, so don't try to second guess and put in a speed hack until you've proven that's where the bottleneck is. - Rob Pike
2013/07/29