Page doesn't render properly ?

MIPS Loongson2 events

This is a list of MIPS Loongson2's CPU's performance counter event types. Please see Loongson2 RISC Microprocessor Family Reference Manual

NameDescriptionCounters usableUnit mask options
CPU_CLK_UNHALTED Cycles outside of haltstate 0
BRANCH_INSTRUCTIONS Branch instructions 0
JR31_INSTRUCTIONS JR(rs=31) instructions 0
ICACHE_MISSES Instruction cache misses 0
ALU1_ISSUED ALU1 operation issued 0
MEM_ISSUED Memory read/write issued 0
FALU1_ISSUED Float ALU1 operation issued 0
BHT_BRANCH_INSTRUCTIONS BHT prediction instructions 0
MEM_READ Read from primary memory 0
FQUEUE_FULL Fix queue full 0
ROQ_FULL Reorder queue full 0
CP0_QUEUE_FULL CP0 queue full 0
TLB_REFILL TLB refill exception 0
EXCEPTION Exceptions 0
INTERNAL_EXCEPTION Internal exceptions 0
INSTRUCTION_COMMITTED Instruction committed 1
BRANCHES_MISPREDICTED Branch mispredicted 1
JR_MISPREDICTED JR mispredicted 1
JR31_MISPREDICTED JR31 mispredicted 1
DCACHE_MISSES Data cache misses 1
ALU2_ISSUED ALU2 operation issued 1
FALU2_ISSUED FALU2 operation issued 1
UNCACHED_ACCESS Uncached accesses 1
BHT_MISPREDICTED Branch history table mispredicted 1
MEM_WRITE Write to memory 1
FTQ_FULL Float queue full 1
BRANCH_QUEUE_FULL Branch queue full 1
ITLB_MISSES Instruction TLB misses 1
TOTAL_EXCEPTIONS Total exceptions 1
LOAD_SPECULATION_MISSES Load speculation misses 1
CP0Q_FORWARD_VALID CP0 queue forward valid 1
Optimizations always bust things, because all optimizations are, in the long haul, a form of cheating, and cheaters eventually get caught. - Larry Wall