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MIPS rm9000 events

This is a list of MIPS rm9000's performance counter event types. See RM9000x2 Family User Manual available from pmc-sierra.com

NameDescriptionCounters usableUnit mask options
CYCLES Processor clock cycles all
INSTRUCTIONS_ISSUED Instructions issued all
FP_INSTRUCTIONS_ISSUED Floating-point instructions issued all
INT_INSTRUCTIONS_ISSUED Integer instructions issued all
LOAD_INSTRUCTIONS_ISSUED Load instructions issued all
STORE_INSTRUCTIONS_ISSUED Store instructions issued all
INSTRUCTIONS_DUAL_ISSUED Dual-issued instruction pairs all
BRANCH_MISSPREDICTS Branch mispredictions all
STALL_CYCLES Stall cycles all
L2_CACHE_MISSES L2 cache misses all
ICACHE_MISSES Icache misses all
DCACHE_MISSES Dcache misses all
DTLB_MISSES Data TLB misses all
ITLB_MISSES Instruction TLB misses all
JTLB_INSTRUCTION_MISSES Joint TLB instruction misses all
JTLB_DATA_MISSES Joint TLB data misses all
BRANCHES_TAKEN Branches taken all
BRANCHES_ISSUED Branch instructions issued all
L2_WRITEBACKS L2 cache writebacks all
DCACHE_WRITEBACKS Dcache writebacks all
DCACHE_MISS_STALL_CYCLES Dcache-miss stall cycles all
CACHE_REMISSES Cache remisses all
FP_POSSIBLE_EXCEPTION_CYCLES Floating-point possible exception cycles all
MULTIPLIER_BUSY_SLIP_CYCLES Slip cycles due to busy multiplier all
COP0_SLIP_CYCLES Co-processor 0 slip cycles all
NONBLOCKING_LOAD_SLIP_CYCLES Slip cycles due to pending non-blocking loads all
WRITE_BUFFER_FULL_STALL_CYCLES Stall cycles due to a full write buffer all
CACHE_INSN_STALL_CYCLES Stall cycles due to cache instructions all
NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES Stall cycles due to pending non-blocking loads - stall start of exception all
More computing sins are committed in the name of efficiency (without necessarily achieving it) than for any other single reason - including blind stupidity. - W. A. Wulf
2013/07/29