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PPC 7450 events

This is a list of PPC 7450's performance counter event types. Please see MPC7450 RISC Microprocessor Family Reference Manual, Chapter 11: Performance Monitor. Downloadable from freescale.com

NameDescriptionCounters usableUnit mask options
CYCLES Processor cycles 0, 1, 2, 3
COMPLETED_INSNS Completed Instructions 0, 1, 2, 3
TBL_BIT_TRANSTNS TBL Bit Transitions 0, 1, 2, 3
DISPATCHED_INSNS Dispatched Instructions 0, 1, 2, 3
PROC_PERFMON_EXC Process Performance Monitor Exception 0, 1, 2, 3
VPU_INSNS VPU Instructions Completed 0, 1, 3
VFPU_INSNS VFPU Instructions Completed 0, 1, 3
VIU1_INSNS VIU1 Instructions Completed 0, 1, 3
VIU2_INSNS VIU2 Instructions Completed 0, 1, 3
VPU_CYCLES Cycles a VPU Instruction 0, 1
VFPU_CYCLES Cycles a VFPU Instruction 0, 1
VIU1_CYCLES Cycles a VIU1 Instruction 0, 1
VIU2_CYCLES Cycles a VIU2 Instruction 0, 1
DTLB_MISSES DTLB misses 2
STORE_INSNS Store Instructions 0, 1
L1_ICACHE_MISSES L1 Instruction Cache Misses 0, 1
L1_DATA_SNOOPS L1 Data Snoops 0, 1
UNRESOLVED_BRANCHES Unresolved Branches 0, 1
MISPREDICTED_BRANCHES Mispredicted branches 3
FOLDED_BRANCHES Folded branches 3
BR_LN_STACK_MIS Branch Link Stack Mispredicted 2
ITLB_TABLE_CYCLES ITLM Hardware Table Search Cycles 0
L1_ICACHE_ACCESSES L1 Instruction Cache Accesses 0
INSN_BP_MATCHES Instruction Breakpoint Matches 0
L1_DSNOOP_HITS L1 data snoop hits 0
WRITETHRU_STORES Write-through stores 0
CACHEINH_STORES Cache-inhibited stores 0
L1_DLOAD_HIT L1 data load hit 0
L1_DTOUCH_HIT L1 data touch hit 0
L1_DSTORE_HIT L1 data store hit 0
L1_DATA_HITS L1 data total hits 0
ALTIVEC_LD_INSNS_COMPLETED Altivec load instructions completed 0
FP_STORE_INSNS_COMPLETED_LSU Floating point store instructions completed in LSU 0
FP_LOAD_INSNS_COMPLETED_LSU Floating point load instructions completed in LSU 0
FP_LDSINGLE_INSNS_COMPLETED_LSU Floating point load single instructions completed in LSU 0
FP_DENORMALIZED_RESULT Floating point denormalized result 0
Bottlenecks occur in surprising places, so don't try to second guess and put in a speed hack until you've proven that's where the bottleneck is. - Rob Pike
2014/09/12