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ppc64 970MP events

This is a list of all ppc64 970MP's performance counter event types.

NameDescriptionCounters usableGroup
CYCLES Processor Cycles 1
PM_RUN_CYC_GRP1 Run cycles 0 Group 1 pm_slice0
PM_CYC_GRP1 Processor cycles 1 Group 1 pm_slice0
PM_STOP_COMPLETION_GRP1 Completion stopped 2 Group 1 pm_slice0
PM_INST_CMPL_GRP1 Instructions completed 3 Group 1 pm_slice0
PM_1PLUS_PPC_CMPL_GRP1 One or more PPC instruction completed 4 Group 1 pm_slice0
PM_CYC_GRP1 Processor cycles 5 Group 1 pm_slice0
PM_GRP_CMPL_GRP1 Group completed 6 Group 1 pm_slice0
PM_GRP_DISP_REJECT_GRP1 Group dispatch rejected 7 Group 1 pm_slice0
PM_CYC_GRP2 Processor cycles 0 Group 2 pm_eprof
PM_CYC_GRP2 Processor cycles 1 Group 2 pm_eprof
PM_LD_MISS_L1_GRP2 L1 D cache load misses 2 Group 2 pm_eprof
PM_DC_INV_L2_GRP2 L1 D cache entries invalidated from L2 3 Group 2 pm_eprof
PM_INST_DISP_GRP2 Instructions dispatched 4 Group 2 pm_eprof
PM_INST_CMPL_GRP2 Instructions completed 5 Group 2 pm_eprof
PM_ST_REF_L1_GRP2 L1 D cache store references 6 Group 2 pm_eprof
PM_LD_REF_L1_GRP2 L1 D cache load references 7 Group 2 pm_eprof
PM_INST_CMPL_GRP3 Instructions completed 0 Group 3 pm_basic
PM_CYC_GRP3 Processor cycles 1 Group 3 pm_basic
PM_LD_MISS_L1_GRP3 L1 D cache load misses 2 Group 3 pm_basic
PM_DC_INV_L2_GRP3 L1 D cache entries invalidated from L2 3 Group 3 pm_basic
PM_INST_DISP_GRP3 Instructions dispatched 4 Group 3 pm_basic
PM_INST_CMPL_GRP3 Instructions completed 5 Group 3 pm_basic
PM_ST_REF_L1_GRP3 L1 D cache store references 6 Group 3 pm_basic
PM_LD_REF_L1_GRP3 L1 D cache load references 7 Group 3 pm_basic
PM_LSU_FLUSH_ULD_GRP4 LRQ unaligned load flushes 0 Group 4 pm_lsu
PM_LSU_FLUSH_UST_GRP4 SRQ unaligned store flushes 1 Group 4 pm_lsu
PM_CYC_GRP4 Processor cycles 2 Group 4 pm_lsu
PM_INST_CMPL_GRP4 Instructions completed 3 Group 4 pm_lsu
PM_LSU_FLUSH_SRQ_GRP4 SRQ flushes 4 Group 4 pm_lsu
PM_LSU_FLUSH_LRQ_GRP4 LRQ flushes 5 Group 4 pm_lsu
PM_ST_REF_L1_GRP4 L1 D cache store references 6 Group 4 pm_lsu
PM_LD_REF_L1_GRP4 L1 D cache load references 7 Group 4 pm_lsu
PM_FPU_FDIV_GRP5 FPU executed FDIV instruction 0 Group 5 pm_fpu1
PM_FPU_FMA_GRP5 FPU executed multiply-add instruction 1 Group 5 pm_fpu1
PM_FPU_FEST_GRP5 FPU executed FEST instruction 2 Group 5 pm_fpu1
PM_FPU_FIN_GRP5 FPU produced a result 3 Group 5 pm_fpu1
PM_CYC_GRP5 Processor cycles 4 Group 5 pm_fpu1
PM_FPU_FSQRT_GRP5 FPU executed FSQRT instruction 5 Group 5 pm_fpu1
PM_INST_CMPL_GRP5 Instructions completed 6 Group 5 pm_fpu1
PM_FPU_FMOV_FEST_GRP5 FPU executing FMOV or FEST instructions 7 Group 5 pm_fpu1
PM_FPU_DENORM_GRP6 FPU received denormalized data 0 Group 6 pm_fpu2
PM_FPU_STALL3_GRP6 FPU stalled in pipe3 1 Group 6 pm_fpu2
PM_CYC_GRP6 Processor cycles 2 Group 6 pm_fpu2
PM_INST_CMPL_GRP6 Instructions completed 3 Group 6 pm_fpu2
PM_FPU_ALL_GRP6 FPU executed add, mult, sub, cmp or sel instruction 4 Group 6 pm_fpu2
PM_FPU_STF_GRP6 FPU executed store instruction 5 Group 6 pm_fpu2
PM_FPU_FRSP_FCONV_GRP6 FPU executed FRSP or FCONV instructions 6 Group 6 pm_fpu2
PM_LSU_LDF_GRP6 LSU executed Floating Point load instruction 7 Group 6 pm_fpu2
PM_XER_MAP_FULL_CYC_GRP7 Cycles XER mapper full 0 Group 7 pm_isu_rename
PM_CR_MAP_FULL_CYC_GRP7 Cycles CR logical operation mapper full 1 Group 7 pm_isu_rename
PM_CRQ_FULL_CYC_GRP7 Cycles CR issue queue full 2 Group 7 pm_isu_rename
PM_GRP_DISP_BLK_SB_CYC_GRP7 Cycles group dispatch blocked by scoreboard 3 Group 7 pm_isu_rename
PM_LR_CTR_MAP_FULL_CYC_GRP7 Cycles LR/CTR mapper full 4 Group 7 pm_isu_rename
PM_INST_DISP_GRP7 Instructions dispatched 5 Group 7 pm_isu_rename
PM_INST_CMPL_GRP7 Instructions completed 6 Group 7 pm_isu_rename
PM_CYC_GRP7 Processor cycles 7 Group 7 pm_isu_rename
PM_FPU0_FULL_CYC_GRP8 Cycles FPU0 issue queue full 0 Group 8 pm_isu_queues1
PM_FPU1_FULL_CYC_GRP8 Cycles FPU1 issue queue full 1 Group 8 pm_isu_queues1
PM_FXLS0_FULL_CYC_GRP8 Cycles FXU0/LS0 queue full 2 Group 8 pm_isu_queues1
PM_FXLS1_FULL_CYC_GRP8 Cycles FXU1/LS1 queue full 3 Group 8 pm_isu_queues1
PM_CYC_GRP8 Processor cycles 4 Group 8 pm_isu_queues1
PM_INST_CMPL_GRP8 Instructions completed 5 Group 8 pm_isu_queues1
PM_LSU_LRQ_FULL_CYC_GRP8 Cycles LRQ full 6 Group 8 pm_isu_queues1
PM_LSU_SRQ_FULL_CYC_GRP8 Cycles SRQ full 7 Group 8 pm_isu_queues1
PM_INST_DISP_GRP9 Instructions dispatched 0 Group 9 pm_isu_flow
PM_CYC_GRP9 Processor cycles 1 Group 9 pm_isu_flow
PM_FXU0_FIN_GRP9 FXU0 produced a result 2 Group 9 pm_isu_flow
PM_FXU1_FIN_GRP9 FXU1 produced a result 3 Group 9 pm_isu_flow
PM_GRP_DISP_VALID_GRP9 Group dispatch valid 4 Group 9 pm_isu_flow
PM_GRP_DISP_REJECT_GRP9 Group dispatch rejected 5 Group 9 pm_isu_flow
PM_INST_CMPL_GRP9 Instructions completed 6 Group 9 pm_isu_flow
PM_CYC_GRP9 Processor cycles 7 Group 9 pm_isu_flow
PM_GCT_EMPTY_CYC_GRP10 Cycles GCT empty 0 Group 10 pm_isu_work
PM_WORK_HELD_GRP10 Work held 1 Group 10 pm_isu_work
PM_STOP_COMPLETION_GRP10 Completion stopped 2 Group 10 pm_isu_work
PM_EE_OFF_EXT_INT_GRP10 Cycles MSR(EE) bit off and external interrupt pending 3 Group 10 pm_isu_work
PM_CYC_GRP10 Processor cycles 4 Group 10 pm_isu_work
PM_INST_CMPL_GRP10 Instructions completed 5 Group 10 pm_isu_work
PM_EE_OFF_GRP10 Cycles MSR(EE) bit off 6 Group 10 pm_isu_work
PM_EXT_INT_GRP10 External interrupts 7 Group 10 pm_isu_work
PM_FPU0_FDIV_GRP11 FPU0 executed FDIV instruction 0 Group 11 pm_fpu3
PM_FPU1_FDIV_GRP11 FPU1 executed FDIV instruction 1 Group 11 pm_fpu3
PM_FPU0_FRSP_FCONV_GRP11 FPU0 executed FRSP or FCONV instructions 2 Group 11 pm_fpu3
PM_FPU1_FRSP_FCONV_GRP11 FPU1 executed FRSP or FCONV instructions 3 Group 11 pm_fpu3
PM_FPU0_FMA_GRP11 FPU0 executed multiply-add instruction 4 Group 11 pm_fpu3
PM_FPU1_FMA_GRP11 FPU1 executed multiply-add instruction 5 Group 11 pm_fpu3
PM_INST_CMPL_GRP11 Instructions completed 6 Group 11 pm_fpu3
PM_CYC_GRP11 Processor cycles 7 Group 11 pm_fpu3
PM_FPU0_FSQRT_GRP12 FPU0 executed FSQRT instruction 0 Group 12 pm_fpu4
PM_FPU1_FSQRT_GRP12 FPU1 executed FSQRT instruction 1 Group 12 pm_fpu4
PM_FPU0_FIN_GRP12 FPU0 produced a result 2 Group 12 pm_fpu4
PM_FPU1_FIN_GRP12 FPU1 produced a result 3 Group 12 pm_fpu4
PM_FPU0_ALL_GRP12 FPU0 executed add, mult, sub, cmp or sel instruction 4 Group 12 pm_fpu4
PM_FPU1_ALL_GRP12 FPU1 executed add, mult, sub, cmp or sel instruction 5 Group 12 pm_fpu4
PM_INST_CMPL_GRP12 Instructions completed 6 Group 12 pm_fpu4
PM_CYC_GRP12 Processor cycles 7 Group 12 pm_fpu4
PM_FPU0_DENORM_GRP13 FPU0 received denormalized data 0 Group 13 pm_fpu5
PM_FPU1_DENORM_GRP13 FPU1 received denormalized data 1 Group 13 pm_fpu5
PM_FPU0_FMOV_FEST_GRP13 FPU0 executed FMOV or FEST instructions 2 Group 13 pm_fpu5
PM_FPU1_FMOV_FEST_GRP13 FPU1 executing FMOV or FEST instructions 3 Group 13 pm_fpu5
PM_CYC_GRP13 Processor cycles 4 Group 13 pm_fpu5
PM_INST_CMPL_GRP13 Instructions completed 5 Group 13 pm_fpu5
PM_FPU0_FEST_GRP13 FPU0 executed FEST instruction 6 Group 13 pm_fpu5
PM_FPU1_FEST_GRP13 FPU1 executed FEST instruction 7 Group 13 pm_fpu5
PM_FPU0_STALL3_GRP14 FPU0 stalled in pipe3 0 Group 14 pm_fpu7
PM_FPU1_STALL3_GRP14 FPU1 stalled in pipe3 1 Group 14 pm_fpu7
PM_FPU0_FIN_GRP14 FPU0 produced a result 2 Group 14 pm_fpu7
PM_FPU1_FIN_GRP14 FPU1 produced a result 3 Group 14 pm_fpu7
PM_CYC_GRP14 Processor cycles 4 Group 14 pm_fpu7
PM_INST_CMPL_GRP14 Instructions completed 5 Group 14 pm_fpu7
PM_CYC_GRP14 Processor cycles 6 Group 14 pm_fpu7
PM_FPU0_FPSCR_GRP14 FPU0 executed FPSCR instruction 7 Group 14 pm_fpu7
PM_LSU0_FLUSH_LRQ_GRP15 LSU0 LRQ flushes 0 Group 15 pm_lsu_flush
PM_LSU1_FLUSH_LRQ_GRP15 LSU1 LRQ flushes 1 Group 15 pm_lsu_flush
PM_CYC_GRP15 Processor cycles 2 Group 15 pm_lsu_flush
PM_CYC_GRP15 Processor cycles 3 Group 15 pm_lsu_flush
PM_LSU0_FLUSH_SRQ_GRP15 LSU0 SRQ flushes 4 Group 15 pm_lsu_flush
PM_LSU1_FLUSH_SRQ_GRP15 LSU1 SRQ flushes 5 Group 15 pm_lsu_flush
PM_INST_CMPL_GRP15 Instructions completed 6 Group 15 pm_lsu_flush
PM_CYC_GRP15 Processor cycles 7 Group 15 pm_lsu_flush
PM_LSU0_FLUSH_ULD_GRP16 LSU0 unaligned load flushes 0 Group 16 pm_lsu_load1
PM_LSU1_FLUSH_ULD_GRP16 LSU1 unaligned load flushes 1 Group 16 pm_lsu_load1
PM_LD_REF_L1_LSU0_GRP16 LSU0 L1 D cache load references 2 Group 16 pm_lsu_load1
PM_LD_REF_L1_LSU1_GRP16 LSU1 L1 D cache load references 3 Group 16 pm_lsu_load1
PM_CYC_GRP16 Processor cycles 4 Group 16 pm_lsu_load1
PM_INST_CMPL_GRP16 Instructions completed 5 Group 16 pm_lsu_load1
PM_LD_MISS_L1_LSU0_GRP16 LSU0 L1 D cache load misses 6 Group 16 pm_lsu_load1
PM_LD_MISS_L1_LSU1_GRP16 LSU1 L1 D cache load misses 7 Group 16 pm_lsu_load1
PM_LSU0_FLUSH_UST_GRP17 LSU0 unaligned store flushes 0 Group 17 pm_lsu_store1
PM_LSU1_FLUSH_UST_GRP17 LSU1 unaligned store flushes 1 Group 17 pm_lsu_store1
PM_ST_REF_L1_LSU0_GRP17 LSU0 L1 D cache store references 2 Group 17 pm_lsu_store1
PM_ST_REF_L1_LSU1_GRP17 LSU1 L1 D cache store references 3 Group 17 pm_lsu_store1
PM_CYC_GRP17 Processor cycles 4 Group 17 pm_lsu_store1
PM_INST_CMPL_GRP17 Instructions completed 5 Group 17 pm_lsu_store1
PM_ST_MISS_L1_GRP17 L1 D cache store misses 6 Group 17 pm_lsu_store1
PM_DC_INV_L2_GRP17 L1 D cache entries invalidated from L2 7 Group 17 pm_lsu_store1
PM_LSU0_SRQ_STFWD_GRP18 LSU0 SRQ store forwarded 0 Group 18 pm_lsu_store2
PM_LSU1_SRQ_STFWD_GRP18 LSU1 SRQ store forwarded 1 Group 18 pm_lsu_store2
PM_ST_REF_L1_LSU0_GRP18 LSU0 L1 D cache store references 2 Group 18 pm_lsu_store2
PM_ST_REF_L1_LSU1_GRP18 LSU1 L1 D cache store references 3 Group 18 pm_lsu_store2
PM_LSU0_BUSY_GRP18 LSU0 busy 4 Group 18 pm_lsu_store2
PM_CYC_GRP18 Processor cycles 5 Group 18 pm_lsu_store2
PM_INST_CMPL_GRP18 Instructions completed 6 Group 18 pm_lsu_store2
PM_CYC_GRP18 Processor cycles 7 Group 18 pm_lsu_store2
PM_LSU0_DERAT_MISS_GRP19 LSU0 DERAT misses 0 Group 19 pm_lsu7
PM_LSU1_DERAT_MISS_GRP19 LSU1 DERAT misses 1 Group 19 pm_lsu7
PM_CYC_GRP19 Processor cycles 2 Group 19 pm_lsu7
PM_CYC_GRP19 Processor cycles 3 Group 19 pm_lsu7
PM_INST_CMPL_GRP19 Instructions completed 4 Group 19 pm_lsu7
PM_CYC_GRP19 Processor cycles 5 Group 19 pm_lsu7
PM_L1_DCACHE_RELOAD_VALID_GRP19 L1 reload data source valid 6 Group 19 pm_lsu7
PM_CYC_GRP19 Processor cycles 7 Group 19 pm_lsu7
PM_GCT_EMPTY_CYC_GRP20 Cycles GCT empty 0 Group 20 pm_misc
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP20 Cycles LMQ and SRQ empty 1 Group 20 pm_misc
PM_HV_CYC_GRP20 Hypervisor Cycles 2 Group 20 pm_misc
PM_CYC_GRP20 Processor cycles 3 Group 20 pm_misc
PM_1PLUS_PPC_CMPL_GRP20 One or more PPC instruction completed 4 Group 20 pm_misc
PM_INST_CMPL_GRP20 Instructions completed 5 Group 20 pm_misc
PM_GRP_CMPL_GRP20 Group completed 6 Group 20 pm_misc
PM_TB_BIT_TRANS_GRP20 Time Base bit transition 7 Group 20 pm_misc
PM_FPU_FDIV_GRP21 FPU executed FDIV instruction 0 Group 21 pm_pe_bench1
PM_FPU_FMA_GRP21 FPU executed multiply-add instruction 1 Group 21 pm_pe_bench1
PM_FXU_FIN_GRP21 FXU produced a result 2 Group 21 pm_pe_bench1
PM_FPU_FIN_GRP21 FPU produced a result 3 Group 21 pm_pe_bench1
PM_CYC_GRP21 Processor cycles 4 Group 21 pm_pe_bench1
PM_FPU_FSQRT_GRP21 FPU executed FSQRT instruction 5 Group 21 pm_pe_bench1
PM_INST_CMPL_GRP21 Instructions completed 6 Group 21 pm_pe_bench1
PM_FPU_FMOV_FEST_GRP21 FPU executing FMOV or FEST instructions 7 Group 21 pm_pe_bench1
PM_DTLB_MISS_GRP22 Data TLB misses 0 Group 22 pm_pe_bench4
PM_ITLB_MISS_GRP22 Instruction TLB misses 1 Group 22 pm_pe_bench4
PM_LD_MISS_L1_GRP22 L1 D cache load misses 2 Group 22 pm_pe_bench4
PM_ST_MISS_L1_GRP22 L1 D cache store misses 3 Group 22 pm_pe_bench4
PM_CYC_GRP22 Processor cycles 4 Group 22 pm_pe_bench4
PM_INST_CMPL_GRP22 Instructions completed 5 Group 22 pm_pe_bench4
PM_ST_REF_L1_GRP22 L1 D cache store references 6 Group 22 pm_pe_bench4
PM_LD_REF_L1_GRP22 L1 D cache load references 7 Group 22 pm_pe_bench4
PM_DTLB_MISS_GRP23 Data TLB misses 0 Group 23 pm_hpmcount1
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP23 Cycles LMQ and SRQ empty 1 Group 23 pm_hpmcount1
PM_LD_MISS_L1_GRP23 L1 D cache load misses 2 Group 23 pm_hpmcount1
PM_ST_MISS_L1_GRP23 L1 D cache store misses 3 Group 23 pm_hpmcount1
PM_CYC_GRP23 Processor cycles 4 Group 23 pm_hpmcount1
PM_INST_CMPL_GRP23 Instructions completed 5 Group 23 pm_hpmcount1
PM_ST_REF_L1_GRP23 L1 D cache store references 6 Group 23 pm_hpmcount1
PM_LD_REF_L1_GRP23 L1 D cache load references 7 Group 23 pm_hpmcount1
PM_FPU_FDIV_GRP24 FPU executed FDIV instruction 0 Group 24 pm_hpmcount2
PM_FPU_FMA_GRP24 FPU executed multiply-add instruction 1 Group 24 pm_hpmcount2
PM_FPU0_FIN_GRP24 FPU0 produced a result 2 Group 24 pm_hpmcount2
PM_FPU1_FIN_GRP24 FPU1 produced a result 3 Group 24 pm_hpmcount2
PM_CYC_GRP24 Processor cycles 4 Group 24 pm_hpmcount2
PM_FPU_STF_GRP24 FPU executed store instruction 5 Group 24 pm_hpmcount2
PM_INST_CMPL_GRP24 Instructions completed 6 Group 24 pm_hpmcount2
PM_LSU_LDF_GRP24 LSU executed Floating Point load instruction 7 Group 24 pm_hpmcount2
PM_INST_CMPL_GRP25 Instructions completed 0 Group 25 pm_l1andbr
PM_CYC_GRP25 Processor cycles 1 Group 25 pm_l1andbr
PM_LD_MISS_L1_GRP25 L1 D cache load misses 2 Group 25 pm_l1andbr
PM_BR_ISSUED_GRP25 Branches issued 3 Group 25 pm_l1andbr
PM_LSU0_BUSY_GRP25 LSU0 busy 4 Group 25 pm_l1andbr
PM_CYC_GRP25 Processor cycles 5 Group 25 pm_l1andbr
PM_BR_MPRED_CR_GRP25 Branch mispredictions due to CR bit setting 6 Group 25 pm_l1andbr
PM_BR_MPRED_TA_GRP25 Branch mispredictions due to target address 7 Group 25 pm_l1andbr
PM_INST_CMPL_GRP26 Instructions completed 0 Group 26 pm_imix
PM_CYC_GRP26 Processor cycles 1 Group 26 pm_imix
PM_LD_MISS_L1_GRP26 L1 D cache load misses 2 Group 26 pm_imix
PM_BR_ISSUED_GRP26 Branches issued 3 Group 26 pm_imix
PM_CYC_GRP26 Processor cycles 4 Group 26 pm_imix
PM_LSU0_BUSY_GRP26 LSU0 busy 5 Group 26 pm_imix
PM_ST_REF_L1_GRP26 L1 D cache store references 6 Group 26 pm_imix
PM_LD_REF_L1_GRP26 L1 D cache load references 7 Group 26 pm_imix
PM_RUN_CYC_GRP27 Run cycles 0 Group 27 pm_branch
PM_DSLB_MISS_GRP27 Data SLB misses 1 Group 27 pm_branch
PM_BR_ISSUED_GRP27 Branches issued 2 Group 27 pm_branch
PM_BR_MPRED_CR_GRP27 Branch mispredictions due to CR bit setting 3 Group 27 pm_branch
PM_ISLB_MISS_GRP27 Instruction SLB misses 4 Group 27 pm_branch
PM_CYC_GRP27 Processor cycles 5 Group 27 pm_branch
PM_INST_CMPL_GRP27 Instructions completed 6 Group 27 pm_branch
PM_BR_MPRED_TA_GRP27 Branch mispredictions due to target address 7 Group 27 pm_branch
PM_DATA_FROM_L2_GRP28 Data loaded from L2 0 Group 28 pm_data
PM_DATA_FROM_MEM_GRP28 Data loaded from memory 1 Group 28 pm_data
PM_INST_CMPL_GRP28 Instructions completed 2 Group 28 pm_data
PM_CYC_GRP28 Processor cycles 3 Group 28 pm_data
PM_INST_CMPL_GRP28 Instructions completed 4 Group 28 pm_data
PM_CYC_GRP28 Processor cycles 5 Group 28 pm_data
PM_LSU_LMQ_S0_ALLOC_GRP28 LMQ slot 0 allocated 6 Group 28 pm_data
PM_LSU_LMQ_S0_VALID_GRP28 LMQ slot 0 valid 7 Group 28 pm_data
PM_DTLB_MISS_GRP29 Data TLB misses 0 Group 29 pm_tlb
PM_ITLB_MISS_GRP29 Instruction TLB misses 1 Group 29 pm_tlb
PM_INST_CMPL_GRP29 Instructions completed 2 Group 29 pm_tlb
PM_CYC_GRP29 Processor cycles 3 Group 29 pm_tlb
PM_LSU_LRQ_S0_ALLOC_GRP29 LRQ slot 0 allocated 4 Group 29 pm_tlb
PM_LSU_LRQ_S0_VALID_GRP29 LRQ slot 0 valid 5 Group 29 pm_tlb
PM_L1_PREF_GRP29 L1 cache data prefetches 6 Group 29 pm_tlb
PM_L2_PREF_GRP29 L2 cache prefetches 7 Group 29 pm_tlb
PM_INST_FROM_L2_GRP30 Instructions fetched from L2 0 Group 30 pm_isource
PM_INST_FROM_MEM_GRP30 Instruction fetched from memory 1 Group 30 pm_isource
PM_HV_CYC_GRP30 Hypervisor Cycles 2 Group 30 pm_isource
PM_INST_CMPL_GRP30 Instructions completed 3 Group 30 pm_isource
PM_DATA_TABLEWALK_CYC_GRP30 Cycles doing data tablewalks 4 Group 30 pm_isource
PM_CYC_GRP30 Processor cycles 5 Group 30 pm_isource
PM_GRP_CMPL_GRP30 Group completed 6 Group 30 pm_isource
PM_DC_INV_L2_GRP30 L1 D cache entries invalidated from L2 7 Group 30 pm_isource
PM_LSU_SRQ_S0_ALLOC_GRP31 SRQ slot 0 allocated 0 Group 31 pm_sync
PM_LSU_SRQ_S0_VALID_GRP31 SRQ slot 0 valid 1 Group 31 pm_sync
PM_LD_MISS_L1_GRP31 L1 D cache load misses 2 Group 31 pm_sync
PM_LSU_SRQ_SYNC_CYC_GRP31 SRQ sync duration 3 Group 31 pm_sync
PM_INST_CMPL_GRP31 Instructions completed 4 Group 31 pm_sync
PM_INST_CMPL_GRP31 Instructions completed 5 Group 31 pm_sync
PM_CYC_GRP31 Processor cycles 6 Group 31 pm_sync
PM_LD_REF_L1_GRP31 L1 D cache load references 7 Group 31 pm_sync
PM_INST_FROM_L1_GRP32 Instruction fetched from L1 0 Group 32 pm_ierat
PM_INST_CMPL_GRP32 Instructions completed 1 Group 32 pm_ierat
PM_IERAT_XLATE_WR_GRP32 Translation written to ierat 2 Group 32 pm_ierat
PM_CYC_GRP32 Processor cycles 3 Group 32 pm_ierat
PM_INST_CMPL_GRP32 Instructions completed 4 Group 32 pm_ierat
PM_CYC_GRP32 Processor cycles 5 Group 32 pm_ierat
PM_INST_CMPL_GRP32 Instructions completed 6 Group 32 pm_ierat
PM_CYC_GRP32 Processor cycles 7 Group 32 pm_ierat
PM_GCT_EMPTY_CYC_GRP33 Cycles GCT empty 0 Group 33 pm_derat
PM_GRP_DISP_VALID_GRP33 Group dispatch valid 1 Group 33 pm_derat
PM_L1_DCACHE_RELOAD_VALID_GRP33 L1 reload data source valid 2 Group 33 pm_derat
PM_INST_CMPL_GRP33 Instructions completed 3 Group 33 pm_derat
PM_INST_DISP_GRP33 Instructions dispatched 4 Group 33 pm_derat
PM_LSU_DERAT_MISS_GRP33 DERAT misses 5 Group 33 pm_derat
PM_ST_REF_L1_GRP33 L1 D cache store references 6 Group 33 pm_derat
PM_CYC_GRP33 Processor cycles 7 Group 33 pm_derat
PM_MRK_LD_MISS_L1_GRP34 Marked L1 D cache load misses 0 Group 34 pm_mark1
PM_THRESH_TIMEO_GRP34 Threshold timeout 1 Group 34 pm_mark1
PM_CYC_GRP34 Processor cycles 2 Group 34 pm_mark1
PM_MRK_GRP_CMPL_GRP34 Marked group completed 3 Group 34 pm_mark1
PM_GRP_MRK_GRP34 Group marked in IDU 4 Group 34 pm_mark1
PM_MRK_GRP_ISSUED_GRP34 Marked group issued 5 Group 34 pm_mark1
PM_MRK_INST_FIN_GRP34 Marked instruction finished 6 Group 34 pm_mark1
PM_INST_CMPL_GRP34 Instructions completed 7 Group 34 pm_mark1
PM_MRK_GRP_DISP_GRP35 Marked group dispatched 0 Group 35 pm_mark2
PM_MRK_BRU_FIN_GRP35 Marked instruction BRU processing finished 1 Group 35 pm_mark2
PM_CYC_GRP35 Processor cycles 2 Group 35 pm_mark2
PM_MRK_CRU_FIN_GRP35 Marked instruction CRU processing finished 3 Group 35 pm_mark2
PM_GRP_MRK_GRP35 Group marked in IDU 4 Group 35 pm_mark2
PM_MRK_FXU_FIN_GRP35 Marked instruction FXU processing finished 5 Group 35 pm_mark2
PM_MRK_FPU_FIN_GRP35 Marked instruction FPU processing finished 6 Group 35 pm_mark2
PM_MRK_LSU_FIN_GRP35 Marked instruction LSU processing finished 7 Group 35 pm_mark2
PM_MRK_ST_CMPL_GRP36 Marked store instruction completed 0 Group 36 pm_mark3
PM_CYC_GRP36 Processor cycles 1 Group 36 pm_mark3
PM_MRK_ST_CMPL_INT_GRP36 Marked store completed with intervention 2 Group 36 pm_mark3
PM_MRK_GRP_CMPL_GRP36 Marked group completed 3 Group 36 pm_mark3
PM_MRK_GRP_TIMEO_GRP36 Marked group completion timeout 4 Group 36 pm_mark3
PM_MRK_ST_GPS_GRP36 Marked store sent to GPS 5 Group 36 pm_mark3
PM_MRK_LSU_SRQ_INST_VALID_GRP36 Marked instruction valid in SRQ 6 Group 36 pm_mark3
PM_INST_CMPL_GRP36 Instructions completed 7 Group 36 pm_mark3
PM_MRK_ST_MISS_L1_GRP37 Marked L1 D cache store misses 0 Group 37 pm_lsu_mark1
PM_MRK_IMR_RELOAD_GRP37 Marked IMR reloaded 1 Group 37 pm_lsu_mark1
PM_MRK_LSU0_FLUSH_UST_GRP37 LSU0 marked unaligned store flushes 2 Group 37 pm_lsu_mark1
PM_MRK_LSU1_FLUSH_UST_GRP37 LSU1 marked unaligned store flushes 3 Group 37 pm_lsu_mark1
PM_CYC_GRP37 Processor cycles 4 Group 37 pm_lsu_mark1
PM_INST_CMPL_GRP37 Instructions completed 5 Group 37 pm_lsu_mark1
PM_MRK_LSU0_FLUSH_ULD_GRP37 LSU0 marked unaligned load flushes 6 Group 37 pm_lsu_mark1
PM_MRK_LSU1_FLUSH_ULD_GRP37 LSU1 marked unaligned load flushes 7 Group 37 pm_lsu_mark1
PM_MRK_LD_MISS_L1_LSU0_GRP38 LSU0 L1 D cache load misses 0 Group 38 pm_lsu_mark2
PM_MRK_LD_MISS_L1_LSU1_GRP38 LSU1 L1 D cache load misses 1 Group 38 pm_lsu_mark2
PM_MRK_LSU0_FLUSH_LRQ_GRP38 LSU0 marked LRQ flushes 2 Group 38 pm_lsu_mark2
PM_MRK_LSU1_FLUSH_LRQ_GRP38 LSU1 marked LRQ flushes 3 Group 38 pm_lsu_mark2
PM_CYC_GRP38 Processor cycles 4 Group 38 pm_lsu_mark2
PM_INST_CMPL_GRP38 Instructions completed 5 Group 38 pm_lsu_mark2
PM_MRK_LSU0_FLUSH_SRQ_GRP38 LSU0 marked SRQ flushes 6 Group 38 pm_lsu_mark2
PM_MRK_LSU1_FLUSH_SRQ_GRP38 LSU1 marked SRQ flushes 7 Group 38 pm_lsu_mark2
PM_INST_CMPL_GRP39 Instructions completed 0 Group 39 pm_fxu1
PM_INST_CMPL_GRP39 Instructions completed 1 Group 39 pm_fxu1
PM_FXU_FIN_GRP39 FXU produced a result 2 Group 39 pm_fxu1
PM_FXU1_BUSY_FXU0_IDLE_GRP39 FXU1 busy FXU0 idle 3 Group 39 pm_fxu1
PM_FXU_IDLE_GRP39 FXU idle 4 Group 39 pm_fxu1
PM_FXU_BUSY_GRP39 FXU busy 5 Group 39 pm_fxu1
PM_FXU0_BUSY_FXU1_IDLE_GRP39 FXU0 busy FXU1 idle 6 Group 39 pm_fxu1
PM_CYC_GRP39 Processor cycles 7 Group 39 pm_fxu1
PM_INST_CMPL_GRP40 Instructions completed 0 Group 40 pm_fxu2
PM_CYC_GRP40 Processor cycles 1 Group 40 pm_fxu2
PM_FXLS1_FULL_CYC_GRP40 Cycles FXU1/LS1 queue full 2 Group 40 pm_fxu2
PM_FXLS0_FULL_CYC_GRP40 Cycles FXU0/LS0 queue full 3 Group 40 pm_fxu2
PM_FXU_IDLE_GRP40 FXU idle 4 Group 40 pm_fxu2
PM_FXU_BUSY_GRP40 FXU busy 5 Group 40 pm_fxu2
PM_FXU0_FIN_GRP40 FXU0 produced a result 6 Group 40 pm_fxu2
PM_FXU1_FIN_GRP40 FXU1 produced a result 7 Group 40 pm_fxu2
PM_INST_FROM_L1_GRP41 Instruction fetched from L1 0 Group 41 pm_ifu
PM_INST_FROM_MEM_GRP41 Instruction fetched from memory 1 Group 41 pm_ifu
PM_INST_FROM_PREF_GRP41 Instructions fetched from prefetch 2 Group 41 pm_ifu
PM_0INST_FETCH_GRP41 No instructions fetched 3 Group 41 pm_ifu
PM_INST_FETCH_CYC_GRP41 Cycles at least 1 instruction fetched 4 Group 41 pm_ifu
PM_INST_FROM_L25_MOD_GRP41 Instruction fetched from L2.5 modified 5 Group 41 pm_ifu
PM_CYC_GRP41 Processor cycles 6 Group 41 pm_ifu
PM_INST_CMPL_GRP41 Instructions completed 7 Group 41 pm_ifu
PM_LSU0_BUSY_GRP42 LSU0 busy 0 Group 42 pm_cpi_stack1
PM_LSU1_BUSY_GRP42 LSU1 busy 1 Group 42 pm_cpi_stack1
PM_LSU_FLUSH_GRP42 Flush initiated by LSU 2 Group 42 pm_cpi_stack1
PM_FLUSH_LSU_BR_MPRED_GRP42 Flush caused by LSU or branch mispredict 3 Group 42 pm_cpi_stack1
PM_CMPLU_STALL_LSU_GRP42 Completion stall caused by LSU instruction 4 Group 42 pm_cpi_stack1
PM_INST_CMPL_GRP42 Instructions completed 5 Group 42 pm_cpi_stack1
PM_CMPLU_STALL_ERAT_MISS_GRP42 Completion stall caused by ERAT miss 6 Group 42 pm_cpi_stack1
PM_CYC_GRP42 Processor cycles 7 Group 42 pm_cpi_stack1
PM_CMPLU_STALL_OTHER_GRP43 Completion stall caused by other reason 0 Group 43 pm_cpi_stack2
PM_INST_CMPL_GRP43 Instructions completed 1 Group 43 pm_cpi_stack2
PM_LD_MISS_L1_GRP43 L1 D cache load misses 2 Group 43 pm_cpi_stack2
PM_CYC_GRP43 Processor cycles 3 Group 43 pm_cpi_stack2
PM_CMPLU_STALL_DCACHE_MISS_GRP43 Completion stall caused by D cache miss 4 Group 43 pm_cpi_stack2
PM_LSU_DERAT_MISS_GRP43 DERAT misses 5 Group 43 pm_cpi_stack2
PM_CMPLU_STALL_REJECT_GRP43 Completion stall caused by reject 6 Group 43 pm_cpi_stack2
PM_LD_REF_L1_GRP43 L1 D cache load references 7 Group 43 pm_cpi_stack2
PM_INST_CMPL_GRP44 Instructions completed 0 Group 44 pm_cpi_stack3
PM_GCT_EMPTY_SRQ_FULL_GRP44 GCT empty caused by SRQ full 1 Group 44 pm_cpi_stack3
PM_FXU_FIN_GRP44 FXU produced a result 2 Group 44 pm_cpi_stack3
PM_FPU_FIN_GRP44 FPU produced a result 3 Group 44 pm_cpi_stack3
PM_CMPLU_STALL_FXU_GRP44 Completion stall caused by FXU instruction 4 Group 44 pm_cpi_stack3
PM_FXU_BUSY_GRP44 FXU busy 5 Group 44 pm_cpi_stack3
PM_CMPLU_STALL_DIV_GRP44 Completion stall caused by DIV instruction 6 Group 44 pm_cpi_stack3
PM_CYC_GRP44 Processor cycles 7 Group 44 pm_cpi_stack3
PM_FPU_FDIV_GRP45 FPU executed FDIV instruction 0 Group 45 pm_cpi_stack4
PM_FPU_FMA_GRP45 FPU executed multiply-add instruction 1 Group 45 pm_cpi_stack4
PM_INST_CMPL_GRP45 Instructions completed 2 Group 45 pm_cpi_stack4
PM_IOPS_CMPL_GRP45 IOPS instructions completed 3 Group 45 pm_cpi_stack4
PM_CMPLU_STALL_FDIV_GRP45 Completion stall caused by FDIV or FQRT instruction 4 Group 45 pm_cpi_stack4
PM_FPU_FSQRT_GRP45 FPU executed FSQRT instruction 5 Group 45 pm_cpi_stack4
PM_CMPLU_STALL_FPU_GRP45 Completion stall caused by FPU instruction 6 Group 45 pm_cpi_stack4
PM_CYC_GRP45 Processor cycles 7 Group 45 pm_cpi_stack4
PM_GCT_EMPTY_CYC_GRP46 Cycles GCT empty 0 Group 46 pm_cpi_stack5
PM_INST_CMPL_GRP46 Instructions completed 1 Group 46 pm_cpi_stack5
PM_FLUSH_BR_MPRED_GRP46 Flush caused by branch mispredict 2 Group 46 pm_cpi_stack5
PM_BR_MPRED_TA_GRP46 Branch mispredictions due to target address 3 Group 46 pm_cpi_stack5
PM_GCT_EMPTY_IC_MISS_GRP46 GCT empty due to I cache miss 4 Group 46 pm_cpi_stack5
PM_CYC_GRP46 Processor cycles 5 Group 46 pm_cpi_stack5
PM_GCT_EMPTY_BR_MPRED_GRP46 GCT empty due to branch mispredict 6 Group 46 pm_cpi_stack5
PM_L1_WRITE_CYC_GRP46 Cycles writing to instruction L1 7 Group 46 pm_cpi_stack5
PM_INST_CMPL_GRP47 Instructions completed 0 Group 47 pm_data2
PM_INST_CMPL_GRP47 Instructions completed 1 Group 47 pm_data2
PM_CYC_GRP47 Processor cycles 2 Group 47 pm_data2
PM_CYC_GRP47 Processor cycles 3 Group 47 pm_data2
PM_DATA_FROM_L25_SHR_GRP47 Data loaded from L2.5 shared 4 Group 47 pm_data2
PM_DATA_FROM_L25_MOD_GRP47 Data loaded from L2.5 modified 5 Group 47 pm_data2
PM_LSU_LMQ_S0_ALLOC_GRP47 LMQ slot 0 allocated 6 Group 47 pm_data2
PM_LSU_LMQ_S0_VALID_GRP47 LMQ slot 0 valid 7 Group 47 pm_data2
PM_INST_FROM_L2_GRP48 Instructions fetched from L2 0 Group 48 pm_fetch_branch
PM_INST_FROM_MEM_GRP48 Instruction fetched from memory 1 Group 48 pm_fetch_branch
PM_INST_FROM_PREF_GRP48 Instructions fetched from prefetch 2 Group 48 pm_fetch_branch
PM_BR_ISSUED_GRP48 Branches issued 3 Group 48 pm_fetch_branch
PM_CYC_GRP48 Processor cycles 4 Group 48 pm_fetch_branch
PM_INST_CMPL_GRP48 Instructions completed 5 Group 48 pm_fetch_branch
PM_BR_MPRED_CR_GRP48 Branch mispredictions due to CR bit setting 6 Group 48 pm_fetch_branch
PM_BR_MPRED_TA_GRP48 Branch mispredictions due to target address 7 Group 48 pm_fetch_branch
PM_DATA_FROM_L2_GRP49 Data loaded from L2 0 Group 49 pm_l1l2_miss
PM_DATA_FROM_MEM_GRP49 Data loaded from memory 1 Group 49 pm_l1l2_miss
PM_INST_CMPL_GRP49 Instructions completed 2 Group 49 pm_l1l2_miss
PM_LD_MISS_L1_LSU0_GRP49 LSU0 L1 D cache load misses 3 Group 49 pm_l1l2_miss
PM_1PLUS_PPC_CMPL_GRP49 One or more PPC instruction completed 4 Group 49 pm_l1l2_miss
PM_CYC_GRP49 Processor cycles 5 Group 49 pm_l1l2_miss
PM_LD_MISS_L1_LSU1_GRP49 LSU1 L1 D cache load misses 6 Group 49 pm_l1l2_miss
PM_LD_REF_L1_GRP49 L1 D cache load references 7 Group 49 pm_l1l2_miss
PM_DATA_FROM_L2_GRP50 Data loaded from L2 0 Group 50 pm_data_from
PM_DATA_FROM_MEM_GRP50 Data loaded from memory 1 Group 50 pm_data_from
PM_INST_CMPL_GRP50 Instructions completed 2 Group 50 pm_data_from
PM_CYC_GRP50 Processor cycles 3 Group 50 pm_data_from
PM_DATA_FROM_L25_SHR_GRP50 Data loaded from L2.5 shared 4 Group 50 pm_data_from
PM_DATA_FROM_L25_MOD_GRP50 Data loaded from L2.5 modified 5 Group 50 pm_data_from
PM_LD_MISS_L1_LSU1_GRP50 LSU1 L1 D cache load misses 6 Group 50 pm_data_from
PM_LD_REF_L1_GRP50 L1 D cache load references 7 Group 50 pm_data_from
PM_MRK_DATA_FROM_L2_GRP51 Marked data loaded from L2 0 Group 51 pm_mark_data_from
PM_MRK_DATA_FROM_MEM_GRP51 Marked data loaded from memory 1 Group 51 pm_mark_data_from
PM_INST_CMPL_GRP51 Instructions completed 2 Group 51 pm_mark_data_from
PM_CYC_GRP51 Processor cycles 3 Group 51 pm_mark_data_from
PM_MRK_DATA_FROM_L25_SHR_GRP51 Marked data loaded from L2.5 shared 4 Group 51 pm_mark_data_from
PM_MRK_DATA_FROM_L25_MOD_GRP51 Marked data loaded from L2.5 modified 5 Group 51 pm_mark_data_from
PM_MRK_INST_FIN_GRP51 Marked instruction finished 6 Group 51 pm_mark_data_from
PM_MRK_L1_RELOAD_VALID_GRP51 Marked L1 reload data source valid 7 Group 51 pm_mark_data_from
More computing sins are committed in the name of efficiency (without necessarily achieving it) than for any other single reason - including blind stupidity. - W. A. Wulf
2013/07/29