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ppc64 Cell BE events

This is a list of all ppc64 Cell Broadband Engine's performance counter event types.

NameDescriptionCounters usableGroup
Group 0 Processor Cycles (counter
Group 0 SPU Processor Cycles (counter
Group 21 Branch instruction committed. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 21 Branch instruction that caused a misprediction flush is committed. Branch misprediction includes: (1) misprediction of taken or not-taken on conditional branch, (2) misprediction of branch target address on bclr[1] and bcctr[1]. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 21 Instruction buffer empty. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 21 Instruction effective-address-to-real-address translation (I-ERAT) miss. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 21 L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions (see Note 1). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 21 Valid instruction available for dispatch, but dispatch is blocked. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 21 Instruction in pipeline stage EX7 causes a flush. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 21 Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 22 Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 22 Store request counted at the L2 interface. Counts microcoded PPE sequences more than once (see Note 1 for exceptions). (Thread 0 and 1) (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 22 Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 22 L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [optional ]
0x20: PPU Bus Word 1 [default ]
Group 31 Load from MFC memory-mapped I/O (MMIO) space. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 31 Stores to MFC MMIO space. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 31 Request token for even memory bank numbers 0-14. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 31 Receive 8-beat data from the Element Interconnect Bus (EIB). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 31 Send 8-beat data to the EIB. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 31 Send a command to the EIB; includes retried commands. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 31 Cycles between data request and data grant. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 31 The five-entry Non-Cacheable Unit (NCU) Store Command queue not empty. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 32 Cache hit for core interface unit (CIU) loads and stores. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 32 Cache miss for CIU loads and stores. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 32 CIU load miss. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 32 CIU store to Invalid state (miss). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 32 Load word and reserve indexed (lwarx/ldarx) for Thread 0 hits Invalid cache state (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 32 Store word conditional indexed (stwcx/stdcx) for Thread 0 hits Invalid cache state when reservation is set. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 32 All four snoop state machines busy. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Data line claim (dclaim) that received good combined response; includes store/stcx/dcbz to Shared (S), Shared Last (SL),or Tagged (T) cache state; does not include dcbz to Invalid (I) cache state (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Dclaim converted into rwitm; may still not get to the bus if stcx is aborted (see Note 2). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Store to modified (M), modified unsolicited (MU), or exclusive (E) cache state. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 8-entry store queue (STQ) full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Store dispatched to RC machine is acknowledged. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Gatherable store (type = 00000) received from CIU. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Snoop push. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Send intervention from (SL | E) cache state to a destination within the same CBE chip. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Send intervention from (M | MU) cache state to a destination within the same CBE chip. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Respond with Retry to a snooped request due to one of the following conflicts: read-and-claim state machine (RC) full address, castout (CO) congruence class, snoop (SNP) machine full address, all snoop machines busy, directory lockout, or parity error. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Respond with Retry to a snooped request because all snoop machines are busy. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Snooped response causes a cache state transition from (M | MU) to (E | S | T). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Snooped response causes a cache state transition from E to S. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Snooped response causes a cache state transition from (E | SL | S | T) to Invalid (I). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 33 Snooped response causes a cache state transition from (M | MU) to I. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 34 Load and reserve indexed (lwarx/ldarx) for Thread 1 hits Invalid cache state. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 34 Store conditional indexed (stwcx/stdcx) for Thread 1 hits Invalid cache state. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 35 Non-cacheable store request received from CIU; includes all synchronization operations such as sync and eieio. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 sync received from CIU. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 Non-cacheable store request received from CIU; includes only stores. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 eieio received from CIU. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 tlbie received from CIU. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 sync at the bottom of the store queue, while waiting on st_done signal from the Bus Interface Unit (BIU) and sync_done signal from L2. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 lwsync at the bottom of the store queue, while waiting for a sync_done signal from the L2. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 eieio at the bottom of the store queue, while waiting for a st_done signal from the BIU and a sync_done signal from the L2. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 tlbie at the bottom of the store queue, while waiting for a st_done signal from the BIU. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 Non-cacheable store combined with the previous non-cacheable store with a contiguous address. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 Load request canceled by CIU due to late detection of load-hit-store condition (128B boundary). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 NCU detects a load hitting a previous store to an overlapping address (32B boundary). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 All four store-gather buffers full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 Non-cacheable load request received from CIU; includes instruction and data fetches. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 The four-deep store queue not empty. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 The four-deep store queue full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 35 At least one store gather buffer not empty. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 41 Dual instruction committed. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Single instruction committed. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Pipeline 0 instruction committed. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Pipeline 1 instruction committed. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Instruction fetch stall. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Local storage busy. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 DMA may conflict with load or store. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Store instruction to local storage issued. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Load intruction from local storage issued. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Floating-Point Unit (FPU) exception. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Branch instruction committed. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Non-sequential change of the SPU program counter, which can be caused by branch, asynchronous interrupt, stalled wait on channel, error correction code (ECC) error, and so forth. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Branch not taken. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Branch miss prediction; not exact. Certain other code sequences can cause additional pulses on this signal (see Note 2). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Branch hint miss prediction; not exact. Certain other code sequences can cause additional pulses on this signal (see Note 2). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Instruction sequence error. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on any blocking channel write (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on External Event Status (Channel 0) (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on Signal Notification 1 (Channel 3) (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on Signal Notification 2 (Channel 4) (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on DMA Command Opcode or ClassID Register (Channel 21) (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on Tag Group Status (Channel 24) (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on List Stall-and-Notify Tag Status (Channel 25) (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on PPU Mailbox (Channel 28) (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 41 Stalled waiting on SPU Mailbox (Channel 29) (see Note 3). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x110: SPU Bus Word 0 [default ]
0x140: SPU Bus Word 2 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 42 Stalled waiting on channel operation (See Note 2). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x104: SPU Trigger 0 [default ]
0x114: SPU Trigger 1 [optional ]
0x124: SPU Trigger 2 [optional ]
0x134: SPU Trigger 3 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 43 Instruction fetch stall. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x144: SPU Event 0 [default ]
0x154: SPU Event 1 [optional ]
0x164: SPU Event 2 [optional ]
0x174: SPU Event 3 [optional ]
0x00: SPU 0 [default ]
0x1000: SPU 1 [optional ]
0x2000: SPU 2 [optional ]
0x3000: SPU 3 [optional ]
0x4000: SPU 4 [optional ]
0x5000: SPU 5 [optional ]
0x6000: SPU 6 [optional ]
0x7000: SPU 7 [optional ]
Group 61 (counter Number of read and rwitm commands including atomic AC1 to AC0. (Group 1)
Group 61 (counter Number of dclaim commands including atomic AC1 to AC0. (Group 1)
Group 61 (counter Number of wwk, wwc, and wwf commands from AC1 to AC0. Group 1
Group 61 (counter Number of sync, tlbsync, and eieio commands from AC1 to AC0. Group 1
Group 61 (counter Number of tlbie commands from AC1 to AC0. Group 1
Group 61 (counter Previous adjacent address match PAAM Content Addressable Memory (CAM) hit. (Group 1)
Group 61 (counter PAAM CAM miss. Group 1
Group 61 (counter Command reflected. Group 1
Group 61 (counter Number of read and rwitm commands including atomic AC1 to AC0. (Group 2)
Group 61 (counter Number of dclaim commands including atomic AC1 to AC0. (Group 2)
Group 61 (counter Number of wwk, wwc, and wwf commands from AC1 to AC0. Group 2
Group 61 (counter Number of sync, tlbsync, and eieio commands from AC1 to AC0. Group 2
Group 61 (counter Number of tlbie commands from AC1 to AC0. Group 2
Group 61 (counter PAAM CAM hit. Group 2
Group 61 (counter PAAM CAM miss. Group 2
Group 61 (counter Command reflected. Group 2
Group 62 Local command from SPE 6. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 Local command from SPE 4. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 Local command from SPE 2. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 Local command from SPE 0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 Local command from PPE. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 Local command from SPE 1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 Local command from SPE 3. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 Local command from SPE 5. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 Local command from SPE 7. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from SPE 6. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from SPE 4. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from SPE 2. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from SPE 0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from PPE. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from SPE 1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from SPE 3. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from SPE 5. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1-to-AC0 global command from SPE 7. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1 sends a global command to AC0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC0 reflects a global command back to AC1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 62 AC1 reflects a command back to the bus masters. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Grant on data ring 0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Grant on data ring 1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Grant on data ring 2. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Grant on data ring 3. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Data ring 0 is in use. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Data ring 1 is in use. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Data ring 2 is in use. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Data ring 3 is in use. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 All data rings are idle. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 One data ring is busy. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 Two or three data rings are busy. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 All data rings are busy. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 BIC data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 6 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 4 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 2 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 0 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 MIC data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 PPE data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 1 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 3 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 5 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 7 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 IOC data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 BIC is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 6 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 4 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 2 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 0 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 MIC is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 PPE is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 63 SPE 1 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 BIC data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 6 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 4 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 2 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 0 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 MIC data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 PPE data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 1 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 3 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 5 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 7 data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 IOC data request pending. (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 BIC is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 6 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 4 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 2 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 0 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 MIC is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 PPE is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 1 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 3 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 5 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 SPE 7 is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 IOC is data destination. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 Grant on data ring 0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 Grant on data ring 1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 Grant on data ring 2. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 Grant on data ring 3. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 All data rings are idle. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 One data ring is busy. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 Two or three data rings are busy. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 64 All four data rings are busy. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 651 Even XIO token unused by RAG 0. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Odd XIO token unused by RAG 0. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Even bank token unused by RAG 0. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Odd bank token unused by RAG 0. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Token granted for SPE 0. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Token granted for SPE 1. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Token granted for SPE 2. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Token granted for SPE 3. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Token granted for SPE 4. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Token granted for SPE 5. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Token granted for SPE 6. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 651 Token granted for SPE 7. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 652 Even XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 652 Odd XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 652 Even bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 652 Odd bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 652 Even XIO token wasted by RAG U. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 652 Odd XIO token wasted by RAG U. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 652 Even bank token wasted by RAG U. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 652 Odd bank token wasted by RAG U. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Even XIO token from RAG 0 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Even XIO token from RAG 0 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Even XIO token from RAG 0 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Odd XIO token from RAG 0 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Odd XIO token from RAG 0 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Odd XIO token from RAG 0 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Even bank token from RAG 0 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Even bank token from RAG 0 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Even bank token from RAG 0 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Odd bank token from RAG 0 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Odd bank token from RAG 0 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 653 Odd bank token from RAG 0 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd bank token from RAG U shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Even XIO token from RAG 1 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Even XIO token from RAG 1 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Even XIO token from RAG 1 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd XIO token from RAG 1 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd XIO token from RAG 1 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd XIO token from RAG 1 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Even bank token from RAG 1 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Even bank token from RAG 1 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Even bank token from RAG 1 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd bank token from RAG 1 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd bank token from RAG 1 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd bank token from RAG 1 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Even XIO token from RAG U shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd XIO token from RAG U shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Even bank token from RAG U shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 656 Odd bank token from RAG U shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [mandatory]
Group 657 Even XIO token unused by RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 657 Odd XIO token unused by RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 657 Even bank token unused by RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 657 Odd bank token unused by RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 657 IOIF0 In token unused by RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 657 IOIF0 Out token unused by RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 657 IOIF1 In token unused by RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 657 IOIF1 Out token unused by RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 658 Even XIO token wasted by RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 658 Odd XIO token wasted by RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 658 Even bank token wasted by RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 658 Odd bank token wasted by RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Even XIO token from RAG 2 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Even XIO token from RAG 2 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Even XIO token from RAG 2 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Odd XIO token from RAG 2 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Odd XIO token from RAG 2 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Odd XIO token from RAG 2 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Even bank token from RAG 2 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Even bank token from RAG 2 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Even bank token from RAG 2 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Odd bank token from RAG 2 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Odd bank token from RAG 2 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 659 Odd bank token from RAG 2 shared with RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6510 IOIF0 In token wasted by RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6510 IOIF0 Out token wasted by RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6510 IOIF1 In token wasted by RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6510 IOIF1 Out token wasted by RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6512 Even XIO token wasted by RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6512 Odd XIO token wasted by RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6512 Even bank token wasted by RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6512 Odd bank token wasted by RAG 3 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Even XIO token from RAG 3 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Even XIO token from RAG 3 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Even XIO token from RAG 3 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Odd XIO token from RAG 3 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Odd XIO token from RAG 3 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Odd XIO token from RAG 3 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Even bank token from RAG 3 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Even bank token from RAG 3 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Even bank token from RAG 3 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Odd bank token from RAG 3 shared with RAG 0 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Odd bank token from RAG 3 shared with RAG 1 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 6513 Odd bank token from RAG 3 shared with RAG 2 (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x40: PPU Bus Word 2 [mandatory]
Group 71 XIO1 - Read command queue is empty. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Write command queue is empty. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Read command queue is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - MIC responds with a Retry for a read command because the read command queue is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Write command queue is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - MIC responds with a Retry for a write command because the write command queue is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Read command dispatched; includes high-priority and fast-path reads (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Write command dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Refresh dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Byte-masking write command (data size >= 16 bytes) dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Write command dispatched after a read command was previously dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 71 XIO1 - Read command dispatched after a write command was previously dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Read command queue is empty. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Write command queue is empty. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Read command queue is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - MIC responds with a Retry for a read command because the read command queue is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Write command queue is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - MIC responds with a Retry for a write command because the write command queue is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Read command dispatched; includes high-priority and fast-path reads (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Write command dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Refresh dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Write command dispatched after a read command was previously dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 72 XIO0 - Read command dispatched after a write command was previously dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 73 XIO0 - Write command dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 73 XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 73 XIO0 - Refresh dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 73 XIO0 - Byte-masking write command (data size >= 16 bytes) dispatched (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x30: PPU Bus Word 0/1 [default ]
0xc0: PPU Bus Word 2/3 [optional ]
Group 81 Type A data physical layer group (PLG). Does not include header-only or credit-only data PLGs. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Type B data PLG. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Type A data PLG. Does not include header-only or credit-only PLGs. In IOIF mode, counts CBE store data to I/O device. Does not apply in BIF mode. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Type B data PLG. In IOIF mode, counts CBE store data to an I/O device. Does not apply in BIF mode. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Data PLG. Does not include header-only or credit-only PLGs. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Command PLG (no credit-only PLG). In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/ reflected command or snoop/combined responses. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Type A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Type B data transfer. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Command-credit-only command PLG in either IOIF or BIF mode. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Data-credit-only data PLG sent in either IOIF or BIF mode. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Non-null envelope sent (does not include long envelopes). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Null envelope sent (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 No valid data sent this cycle (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Normal envelope sent (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Long envelope sent (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 A Null PLG inserted in an outgoing envelope. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 81 Outbound envelope array is full. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 82 Type B data transfer. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Null envelope received (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Command PLG, but not credit-only PLG. In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/reflected command or snoop/combined responses. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Command-credit-only command PLG. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Normal envelope received is good (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Long envelope received is good (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Data-credit-only data PLG in either IOIF or BIF mode; will count a maximum of one per envelope (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Non-null envelope; does not include long envelopes; includes retried envelopes (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Data grant received. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Data PLG. Does not include header-only or credit-only PLGs. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Type A data transfer regardless of length. Can also be used to count Type A data header PLGs, but not credit-only PLGs. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 83 Type B data transfer. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Null envelope received (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Command PLG (no credit-only PLG). Counts I/O command or reply PLGs. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Command-credit-only command PLG. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Normal envelope received is good (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Long envelope received is good (see Note 1). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Data-credit-only data PLG received; will count a maximum of one per envelope (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Non-Null envelope received; does not include long envelopes; includes retried envelopes (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Data grant received. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Data PLG received. Does not include header-only or credit-only PLGs. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Type I A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 84 Type B data transfer received. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 85 Received MMIO read targeted to IOIF1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 85 Received MMIO write targeted to IOIF1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 85 Received MMIO read targeted to IOIF0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 85 Received MMIO write targeted to IOIF0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 85 Sent command to IOIF0. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 85 Sent command to IOIF1. (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 86 IOIF0 Dependency Matrix 3 is occupied by a dependent command (see Note 1). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 86 IOIF0 Dependency Matrix 4 is occupied by a dependent command (see Note 1). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 86 IOIF0 Dependency Matrix 5 is occupied by a dependent command (see Note 1). (counter 0x00: Count edges [optional ]
0x01: Count cycles [default ]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 86 Received read request from IOIF0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 86 Received write request from IOIF0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 86 Received interrupt from the IOIF0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 87 IOIF0 request for token for even memory banks 0-14 (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 87 IOIF0 request for token for odd memory banks 1-15 (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 87 IOIF0 request for token type 1, 3, 5, or 7 (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 87 IOIF0 request for token type 9, 11, 13, or 15 (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 87 IOIF0 request for token type 16 (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 87 IOIF0 request for token type 17 (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 87 IOIF0 request for token type 18 (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 87 IOIF0 request for token type 19 (see Note 1). (counter 0x01: Count cycles [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 I/O page table cache hit for commands from IOIF. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 I/O page table cache miss for commands from IOIF. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 I/O segment table cache hit. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 I/O segment table cache miss. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 Interrupt received from any SPU (reflected cmd when IIC has sent ACK response). (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 Internal interrupt controller (IIC) generated interrupt to PPU thread 0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 IIC generated interrupt to PPU thread 1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 Received external interrupt (using MMIO) from PPU to PPU thread 0. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 Received external interrupt (using MMIO) from PPU to PPU thread 1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
Group 88 Received external interrupt (using MMIO) from PPU to PPU thread 1. (counter 0x00: Count edges [mandatory]
0x00: Negative polarity [optional ]
0x02: Positive polarity [default ]
0x10: PPU Bus Word 0 [default ]
0x40: PPU Bus Word 2 [optional ]
A wise man proportions his belief to the evidence. - David Hume
2013/07/29