This is a list of architected performance counter events for newer IBM POWER processors (POWER6 and later).
| Name | Description | Counters usable | Group |
| CYCLES | Processor Cycles | 2 | |
| PM_THRD_ONE_RUN_CYC_GRP1 | At least one thread in run cycles | 0 | Group 1 pm_compat_utilization1 |
| PM_RUN_CYC_GRP1 | Run cycles | 1 | Group 1 pm_compat_utilization1 |
| PM_CYC_GRP1 | Processor cycles | 2 | Group 1 pm_compat_utilization1 |
| PM_RUN_PURR_GRP1 | Run PURR Even | 3 | Group 1 pm_compat_utilization1 |
| PM_FPU_FLOP_GRP2 | FPU executed 1FLOP, FMA, FSQRT or FDIV instruction | 0 | Group 2 pm_compat_utilization2 |
| PM_RUN_CYC_GRP2 | Run cycles | 1 | Group 2 pm_compat_utilization2 |
| PM_CYC_GRP2 | Processor cycles | 2 | Group 2 pm_compat_utilization2 |
| PM_RUN_INST_CMPL_GRP2 | Run instructions completed | 3 | Group 2 pm_compat_utilization2 |
| PM_DATA_FROM_L1-5_GRP3 | Data loaded from L1.5 | 0 | Group 3 pm_compat_dsource |
| PM_DATA_FROM_L2MISS_GRP3 | Data loaded missed L2 | 1 | Group 3 pm_compat_dsource |
| PM_DATA_FROM_L3MISS_GRP3 | Data loaded from private L3 miss | 2 | Group 3 pm_compat_dsource |
| PM_RUN_INST_CMPL_GRP3 | Run instructions completed | 3 | Group 3 pm_compat_dsource |
| PM_INST_CMPL_GRP4 | Instruction completed | 0 | Group 4 pm_compat_l1_dcache_load_store_miss |
| PM_ST_FIN_GRP4 | Store instructions finished | 1 | Group 4 pm_compat_l1_dcache_load_store_miss |
| PM_ST_MISS_L1_GRP4 | L1 D cache store misses | 2 | Group 4 pm_compat_l1_dcache_load_store_miss |
| PM_LD_MISS_L1_GRP4 | L1 D cache load misses | 3 | Group 4 pm_compat_l1_dcache_load_store_miss |
| PM_INST_CMPL_GRP5 | Instruction completed | 0 | Group 5 pm_compat_l1_cache_load |
| PM_DATA_FROM_L2MISS_GRP5 | Data loaded missed L2 | 1 | Group 5 pm_compat_l1_cache_load |
| PM_L1_DCACHE_RELOAD_VALID_GRP5 | L1 reload data source valid | 2 | Group 5 pm_compat_l1_cache_load |
| PM_LD_MISS_L1_GRP5 | L1 D cache load misses | 3 | Group 5 pm_compat_l1_cache_load |
| PM_IERAT_MISS_GRP6 | IERAT miss coun | 0 | Group 6 pm_compat_instruction_directory |
| PM_L1_ICACHE_MISS_GRP6 | L1 I cache miss coun | 1 | Group 6 pm_compat_instruction_directory |
| PM_INST_CMPL_GRP6 | Instruction completed | 2 | Group 6 pm_compat_instruction_directory |
| PM_ITLB_MISS_GRP6 | Instruction TLB misses | 3 | Group 6 pm_compat_instruction_directory |
| PM_LSU_DERAT_MISS_CYC_GRP7 | DERAT miss latency | 0 | Group 7 pm_compat_data_directory |
| PM_LSU_DERAT_MISS_GRP7 | DERAT misses | 1 | Group 7 pm_compat_data_directory |
| PM_DTLB_MISS_GRP7 | Data TLB misses | 2 | Group 7 pm_compat_data_directory |
| PM_RUN_INST_CMPL_GRP7 | Run instructions completed | 3 | Group 7 pm_compat_data_directory |
| PM_1PLUS_PPC_CMPL_GRP8 | One or more PPC instruction completed | 0 | Group 8 pm_compat_cpi_1plus_ppc |
| PM_RUN_CYC_GRP8 | Run cycles | 1 | Group 8 pm_compat_cpi_1plus_ppc |
| PM_INST_DISP_GRP8 | Instructions dispatched | 2 | Group 8 pm_compat_cpi_1plus_ppc |
| PM_1PLUS_PPC_DISP_GRP8 | Cycles at least one instruction dispatched | 3 | Group 8 pm_compat_cpi_1plus_ppc |
| PM_INST_CMPL_GRP9 | Instruction completed | 0 | Group 9 pm_compat_misc_events1 |
| PM_EXT_INT_GRP9 | External interrupts | 1 | Group 9 pm_compat_misc_events1 |
| PM_TB_BIT_TRANS_GRP9 | Time Base bit transition | 2 | Group 9 pm_compat_misc_events1 |
| PM_CYC_GRP9 | Processor cycles | 3 | Group 9 pm_compat_misc_events1 |
| PM_INST_IMC_MATCH_CMPL_GRP10 | IMC matched instructions completed | 0 | Group 10 pm_compat_misc_events2 |
| PM_INST_DISP_GRP10 | Instructions dispatched | 1 | Group 10 pm_compat_misc_events2 |
| PM_THRD_CONC_RUN_INST_GRP10 | Concurrent run instructions | 2 | Group 10 pm_compat_misc_events2 |
| PM_FLUSH_GRP10 | Flushes | 3 | Group 10 pm_compat_misc_events2 |
| PM_GCT_EMPTY_CYC_GRP11 | Cycles GCT empty | 0 | Group 11 pm_compat_misc_events3 |
| PM_INST_DISP_GRP11 | Instructions dispatched | 1 | Group 11 pm_compat_misc_events3 |
| PM_TB_BIT_TRANS_GRP11 | Time Base bit transition | 2 | Group 11 pm_compat_misc_events3 |
| PM_BR_MPRED_GRP11 | Branches incorrectly predicted | 3 | Group 11 pm_compat_misc_events3 |
| PM_SUSPENDED_GRP12 | Suspended | 0 | Group 12 pm_compat_suspend |
| PM_SUSPENDED_GRP12 | Suspended | 1 | Group 12 pm_compat_suspend |
| PM_SUSPENDED_GRP12 | Suspended | 2 | Group 12 pm_compat_suspend |
| PM_SUSPENDED_GRP12 | Suspended | 3 | Group 12 pm_compat_suspend |
Don't speculate - benchmark.- Dan Bernstein