This is a list of all ppc64 PA6T's performance counter event types.
| Name | Description | Counters usable | Group |
| CYCLES | Processor Cycles | 0 | |
| ISS_CYCLES | Processor Cycles with instructions issued | 3 | |
| RET_UOP | Retired Micro-operatioins | 4 | |
| GRP1_CYCLES | Processor Cycles | 0 | |
| GRP1_INST_RETIRED | Instructions retired | 1 | |
| GRP1_DCACHE_RD_MISS__NS | Dcache read misses NS | 2 | |
| GRP1_MRB_LD_MISS_L2__NS | Load misses filling from memory | 3 | |
| GRP1_MRB_ST_MISS_ALLOC__NS | Store misses in L1D and allocates an MRB entry | 4 | |
| GRP1_TLB_MISS_D__NS | TLB misses NS (D- only) | 5 | |
| GRP2_CYCLES | Processor Cycles | 0 | |
| GRP2_INST_RETIRED | Instructions retired | 1 | |
| GRP2_FETCH_REQ | Demand fetch requests made to the Icache | 2 | |
| GRP2_ICACHE_MISS_DEM__NS | Demand fetch requests missing in the Icache | 3 | |
| GRP2_ICACHE_MISS_ALL | Demand and spec fetch requests missing in the Icache | 4 | |
| GRP2_ICACHE_ACC | Icache accesses | 5 | |
| GRP3_CYCLES | Processor Cycles | 0 | |
| GRP3_INST_RETIRED | Instructions retired | 1 | |
| GRP3_NXT_LINE_MISPRED__NS | Next fetch address mispredict | 2 | |
| GRP3_DIRN_MISPRED__NS | Branch direction mispredict | 3 | |
| GRP3_TGT_ADDR_MISPRED__NS | Branch target address mispredict | 4 | |
| GRP3_BRA_TAKEN__NS | Taken branches | 5 | |
| GRP4_CYCLES | Processor Cycles | 0 | |
| GRP4_INST_RETIRED | Instructions retired | 1 | |
| GRP4_TLB_MISS_D__NS | TLB Misses (D-) | 2 | |
| GRP4_TLB_MISS_I__NS | TLB MIsses (I-) | 3 | |
| GRP4_DERAT_MISS__NS | DERAT Misses | 4 | |
| GRP4_IERAT_MISS__NS | IERAT Misses | 5 | |
| GRP5_CYCLES | Processor Cycles | 0 | |
| GRP5_INST_RETIRED | Instructions retired | 1 | |
| GRP5_DCACHE_RD_MISS__NS | Dcache read misses NS | 2 | |
| GRP5_MRB_LD_MISS_L2__NS | Load misses filling from memory | 3 | |
| GRP5_DCACHE_VIC | Dcache line evicted (snoops not included) | 4 | |
| GRP5_MRB_ST_MISS_ALLOC__NS | Store misses in L1D and allocates an MRB entry | 5 |
Bottlenecks occur in surprising places, so don't try to second guess and put in a speed hack until you've proven that's where the bottleneck is.- Rob Pike