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ppc64 POWER4 events

This is a list of all ppc64 POWER4's performance counter event types.

NameDescriptionCounters usableGroup
CYCLES Processor Cycles 1
PM_RUN_CYC_GRP1 Run cycles 0 Group 1 pm_slice0
PM_CYC_GRP1 Processor cycles 1 Group 1 pm_slice0
PM_STOP_COMPLETION_GRP1 Completion stopped 2 Group 1 pm_slice0
PM_INST_CMPL_GRP1 Instructions completed 3 Group 1 pm_slice0
PM_1PLUS_PPC_CMPL_GRP1 One or more PPC instruction completed 4 Group 1 pm_slice0
PM_CYC_GRP1 Processor cycles 5 Group 1 pm_slice0
PM_GRP_CMPL_GRP1 Group completed 6 Group 1 pm_slice0
PM_GRP_DISP_REJECT_GRP1 Group dispatch rejected 7 Group 1 pm_slice0
PM_CYC_GRP2 Processor cycles 0 Group 2 pm_eprof
PM_CYC_GRP2 Processor cycles 1 Group 2 pm_eprof
PM_LD_MISS_L1_GRP2 L1 D cache load misses 2 Group 2 pm_eprof
PM_DC_INV_L2_GRP2 L1 D cache entries invalidated from L2 3 Group 2 pm_eprof
PM_INST_DISP_GRP2 Instructions dispatched 4 Group 2 pm_eprof
PM_INST_CMPL_GRP2 Instructions completed 5 Group 2 pm_eprof
PM_ST_REF_L1_GRP2 L1 D cache store references 6 Group 2 pm_eprof
PM_LD_REF_L1_GRP2 L1 D cache load references 7 Group 2 pm_eprof
PM_INST_CMPL_GRP3 Instructions completed 0 Group 3 pm_basic
PM_CYC_GRP3 Processor cycles 1 Group 3 pm_basic
PM_LD_MISS_L1_GRP3 L1 D cache load misses 2 Group 3 pm_basic
PM_DC_INV_L2_GRP3 L1 D cache entries invalidated from L2 3 Group 3 pm_basic
PM_INST_DISP_GRP3 Instructions dispatched 4 Group 3 pm_basic
PM_INST_CMPL_GRP3 Instructions completed 5 Group 3 pm_basic
PM_ST_REF_L1_GRP3 L1 D cache store references 6 Group 3 pm_basic
PM_LD_REF_L1_GRP3 L1 D cache load references 7 Group 3 pm_basic
PM_INST_CMPL_GRP4 Instructions completed 0 Group 4 pm_ifu
PM_BIQ_IDU_FULL_CYC_GRP4 Cycles BIQ or IDU full 1 Group 4 pm_ifu
PM_BR_ISSUED_GRP4 Branches issued 2 Group 4 pm_ifu
PM_BR_MPRED_CR_GRP4 Branch mispredictions due CR bit setting 3 Group 4 pm_ifu
PM_INST_FETCH_CYC_GRP4 Cycles at least 1 instruction fetched 4 Group 4 pm_ifu
PM_CYC_GRP4 Processor cycles 5 Group 4 pm_ifu
PM_BR_MPRED_TA_GRP4 Branch mispredictions due to target address 6 Group 4 pm_ifu
PM_L1_WRITE_CYC_GRP4 Cycles writing to instruction L1 7 Group 4 pm_ifu
PM_FPR_MAP_FULL_CYC_GRP5 Cycles FPR mapper full 0 Group 5 pm_isu
PM_BRQ_FULL_CYC_GRP5 Cycles branch queue full 1 Group 5 pm_isu
PM_GPR_MAP_FULL_CYC_GRP5 Cycles GPR mapper full 2 Group 5 pm_isu
PM_INST_CMPL_GRP5 Instructions completed 3 Group 5 pm_isu
PM_FPU_FULL_CYC_GRP5 Cycles FPU issue queue full 4 Group 5 pm_isu
PM_GCT_FULL_CYC_GRP5 Cycles GCT full 5 Group 5 pm_isu
PM_CYC_GRP5 Processor cycles 6 Group 5 pm_isu
PM_FXLS_FULL_CYC_GRP5 Cycles FXLS queue is full 7 Group 5 pm_isu
PM_DATA_FROM_L3_GRP6 Data loaded from L3 0 Group 6 pm_lsource
PM_DATA_FROM_MEM_GRP6 Data loaded from memory 1 Group 6 pm_lsource
PM_DATA_FROM_L35_GRP6 Data loaded from L3.5 2 Group 6 pm_lsource
PM_DATA_FROM_L2_GRP6 Data loaded from L2 3 Group 6 pm_lsource
PM_DATA_FROM_L25_SHR_GRP6 Data loaded from L2.5 shared 4 Group 6 pm_lsource
PM_DATA_FROM_L275_SHR_GRP6 Data loaded from L2.75 shared 5 Group 6 pm_lsource
PM_DATA_FROM_L275_MOD_GRP6 Data loaded from L2.75 modified 6 Group 6 pm_lsource
PM_DATA_FROM_L25_MOD_GRP6 Data loaded from L2.5 modified 7 Group 6 pm_lsource
PM_INST_FROM_MEM_GRP7 Instruction fetched from memory 0 Group 7 pm_isource
PM_INST_FROM_L25_L275_GRP7 Instruction fetched from L2.5/L2.75 1 Group 7 pm_isource
PM_INST_FROM_L2_GRP7 Instructions fetched from L2 2 Group 7 pm_isource
PM_INST_FROM_L35_GRP7 Instructions fetched from L3.5 3 Group 7 pm_isource
PM_INST_FROM_L3_GRP7 Instruction fetched from L3 4 Group 7 pm_isource
PM_INST_FROM_L1_GRP7 Instruction fetched from L1 5 Group 7 pm_isource
PM_INST_FROM_PREF_GRP7 Instructions fetched from prefetch 6 Group 7 pm_isource
PM_0INST_FETCH_GRP7 No instructions fetched 7 Group 7 pm_isource
PM_LSU_FLUSH_ULD_GRP8 LRQ unaligned load flushes 0 Group 8 pm_lsu
PM_LSU_FLUSH_UST_GRP8 SRQ unaligned store flushes 1 Group 8 pm_lsu
PM_CYC_GRP8 Processor cycles 2 Group 8 pm_lsu
PM_INST_CMPL_GRP8 Instructions completed 3 Group 8 pm_lsu
PM_LSU_FLUSH_SRQ_GRP8 SRQ flushes 4 Group 8 pm_lsu
PM_LSU_FLUSH_LRQ_GRP8 LRQ flushes 5 Group 8 pm_lsu
PM_ST_REF_L1_GRP8 L1 D cache store references 6 Group 8 pm_lsu
PM_LD_REF_L1_GRP8 L1 D cache load references 7 Group 8 pm_lsu
PM_ITLB_MISS_GRP9 Instruction TLB misses 0 Group 9 pm_xlate1
PM_DTLB_MISS_GRP9 Data TLB misses 1 Group 9 pm_xlate1
PM_DATA_TABLEWALK_CYC_GRP9 Cycles doing data tablewalks 2 Group 9 pm_xlate1
PM_LSU_LMQ_S0_VALID_GRP9 LMQ slot 0 valid 3 Group 9 pm_xlate1
PM_IERAT_XLATE_WR_GRP9 Translation written to ierat 4 Group 9 pm_xlate1
PM_LSU_DERAT_MISS_GRP9 DERAT misses 5 Group 9 pm_xlate1
PM_INST_CMPL_GRP9 Instructions completed 6 Group 9 pm_xlate1
PM_CYC_GRP9 Processor cycles 7 Group 9 pm_xlate1
PM_ISLB_MISS_GRP10 Instruction SLB misses 0 Group 10 pm_xlate2
PM_DSLB_MISS_GRP10 Data SLB misses 1 Group 10 pm_xlate2
PM_LSU_SRQ_SYNC_CYC_GRP10 SRQ sync duration 2 Group 10 pm_xlate2
PM_LSU_LMQ_S0_ALLOC_GRP10 LMQ slot 0 allocated 3 Group 10 pm_xlate2
PM_IERAT_XLATE_WR_GRP10 Translation written to ierat 4 Group 10 pm_xlate2
PM_LSU_DERAT_MISS_GRP10 DERAT misses 5 Group 10 pm_xlate2
PM_INST_CMPL_GRP10 Instructions completed 6 Group 10 pm_xlate2
PM_CYC_GRP10 Processor cycles 7 Group 10 pm_xlate2
PM_L3B0_DIR_REF_GRP11 L3 bank 0 directory references 0 Group 11 pm_gps1
PM_L3B0_DIR_MIS_GRP11 L3 bank 0 directory misses 1 Group 11 pm_gps1
PM_FAB_CMD_ISSUED_GRP11 Fabric command issued 2 Group 11 pm_gps1
PM_FAB_CMD_RETRIED_GRP11 Fabric command retried 3 Group 11 pm_gps1
PM_L3B1_DIR_REF_GRP11 L3 bank 1 directory references 4 Group 11 pm_gps1
PM_L3B1_DIR_MIS_GRP11 L3 bank 1 directory misses 5 Group 11 pm_gps1
PM_INST_CMPL_GRP11 Instructions completed 6 Group 11 pm_gps1
PM_CYC_GRP11 Processor cycles 7 Group 11 pm_gps1
PM_L2SA_MOD_TAG_GRP12 L2 slice A transition from modified to tagged 0 Group 12 pm_l2a
PM_L2SA_SHR_INV_GRP12 L2 slice A transition from shared to invalid 1 Group 12 pm_l2a
PM_L2SA_ST_REQ_GRP12 L2 slice A store requests 2 Group 12 pm_l2a
PM_L2SA_ST_HIT_GRP12 L2 slice A store hits 3 Group 12 pm_l2a
PM_L2SA_SHR_MOD_GRP12 L2 slice A transition from shared to modified 4 Group 12 pm_l2a
PM_L2SA_MOD_INV_GRP12 L2 slice A transition from modified to invalid 5 Group 12 pm_l2a
PM_INST_CMPL_GRP12 Instructions completed 6 Group 12 pm_l2a
PM_CYC_GRP12 Processor cycles 7 Group 12 pm_l2a
PM_L2SB_MOD_TAG_GRP13 L2 slice B transition from modified to tagged 0 Group 13 pm_l2b
PM_L2SB_SHR_INV_GRP13 L2 slice B transition from shared to invalid 1 Group 13 pm_l2b
PM_L2SB_ST_REQ_GRP13 L2 slice B store requests 2 Group 13 pm_l2b
PM_L2SB_ST_HIT_GRP13 L2 slice B store hits 3 Group 13 pm_l2b
PM_L2SB_SHR_MOD_GRP13 L2 slice B transition from shared to modified 4 Group 13 pm_l2b
PM_L2SB_MOD_INV_GRP13 L2 slice B transition from modified to invalid 5 Group 13 pm_l2b
PM_INST_CMPL_GRP13 Instructions completed 6 Group 13 pm_l2b
PM_CYC_GRP13 Processor cycles 7 Group 13 pm_l2b
PM_L2SC_MOD_TAG_GRP14 L2 slice C transition from modified to tagged 0 Group 14 pm_l2c
PM_L2SC_SHR_INV_GRP14 L2 slice C transition from shared to invalid 1 Group 14 pm_l2c
PM_L2SC_ST_REQ_GRP14 L2 slice C store requests 2 Group 14 pm_l2c
PM_L2SC_ST_HIT_GRP14 L2 slice C store hits 3 Group 14 pm_l2c
PM_L2SC_SHR_MOD_GRP14 L2 slice C transition from shared to modified 4 Group 14 pm_l2c
PM_L2SC_MOD_INV_GRP14 L2 slice C transition from modified to invalid 5 Group 14 pm_l2c
PM_INST_CMPL_GRP14 Instructions completed 6 Group 14 pm_l2c
PM_CYC_GRP14 Processor cycles 7 Group 14 pm_l2c
PM_FPU_FDIV_GRP15 FPU executed FDIV instruction 0 Group 15 pm_fpu1
PM_FPU_FMA_GRP15 FPU executed multiply-add instruction 1 Group 15 pm_fpu1
PM_FPU_FEST_GRP15 FPU executed FEST instruction 2 Group 15 pm_fpu1
PM_FPU_FIN_GRP15 FPU produced a result 3 Group 15 pm_fpu1
PM_CYC_GRP15 Processor cycles 4 Group 15 pm_fpu1
PM_FPU_FSQRT_GRP15 FPU executed FSQRT instruction 5 Group 15 pm_fpu1
PM_INST_CMPL_GRP15 Instructions completed 6 Group 15 pm_fpu1
PM_FPU_FMOV_FEST_GRP15 FPU executing FMOV or FEST instructions 7 Group 15 pm_fpu1
PM_FPU_DENORM_GRP16 FPU received denormalized data 0 Group 16 pm_fpu2
PM_FPU_STALL3_GRP16 FPU stalled in pipe3 1 Group 16 pm_fpu2
PM_CYC_GRP16 Processor cycles 2 Group 16 pm_fpu2
PM_INST_CMPL_GRP16 Instructions completed 3 Group 16 pm_fpu2
PM_FPU_ALL_GRP16 FPU executed add, mult, sub, cmp or sel instruction 4 Group 16 pm_fpu2
PM_FPU_STF_GRP16 FPU executed store instruction 5 Group 16 pm_fpu2
PM_FPU_FRSP_FCONV_GRP16 FPU executed FRSP or FCONV instructions 6 Group 16 pm_fpu2
PM_LSU_LDF_GRP16 LSU executed Floating Point load instruction 7 Group 16 pm_fpu2
PM_INST_CMPL_GRP17 Instructions completed 0 Group 17 pm_idu1
PM_CYC_GRP17 Processor cycles 1 Group 17 pm_idu1
PM_1INST_CLB_CYC_GRP17 Cycles 1 instruction in CLB 2 Group 17 pm_idu1
PM_2INST_CLB_CYC_GRP17 Cycles 2 instructions in CLB 3 Group 17 pm_idu1
PM_1PLUS_PPC_CMPL_GRP17 One or more PPC instruction completed 4 Group 17 pm_idu1
PM_CYC_GRP17 Processor cycles 5 Group 17 pm_idu1
PM_3INST_CLB_CYC_GRP17 Cycles 3 instructions in CLB 6 Group 17 pm_idu1
PM_4INST_CLB_CYC_GRP17 Cycles 4 instructions in CLB 7 Group 17 pm_idu1
PM_INST_CMPL_GRP18 Instructions completed 0 Group 18 pm_idu2
PM_CYC_GRP18 Processor cycles 1 Group 18 pm_idu2
PM_5INST_CLB_CYC_GRP18 Cycles 5 instructions in CLB 2 Group 18 pm_idu2
PM_6INST_CLB_CYC_GRP18 Cycles 6 instructions in CLB 3 Group 18 pm_idu2
PM_GRP_DISP_SUCCESS_GRP18 Group dispatch success 4 Group 18 pm_idu2
PM_CYC_GRP18 Processor cycles 5 Group 18 pm_idu2
PM_7INST_CLB_CYC_GRP18 Cycles 7 instructions in CLB 6 Group 18 pm_idu2
PM_8INST_CLB_CYC_GRP18 Cycles 8 instructions in CLB 7 Group 18 pm_idu2
PM_XER_MAP_FULL_CYC_GRP19 Cycles XER mapper full 0 Group 19 pm_isu_rename
PM_CR_MAP_FULL_CYC_GRP19 Cycles CR logical operation mapper full 1 Group 19 pm_isu_rename
PM_CRQ_FULL_CYC_GRP19 Cycles CR issue queue full 2 Group 19 pm_isu_rename
PM_GRP_DISP_BLK_SB_CYC_GRP19 Cycles group dispatch blocked by scoreboard 3 Group 19 pm_isu_rename
PM_LR_CTR_MAP_FULL_CYC_GRP19 Cycles LR/CTR mapper full 4 Group 19 pm_isu_rename
PM_INST_DISP_GRP19 Instructions dispatched 5 Group 19 pm_isu_rename
PM_INST_CMPL_GRP19 Instructions completed 6 Group 19 pm_isu_rename
PM_CYC_GRP19 Processor cycles 7 Group 19 pm_isu_rename
PM_FPU0_FULL_CYC_GRP20 Cycles FPU0 issue queue full 0 Group 20 pm_isu_queues1
PM_FPU1_FULL_CYC_GRP20 Cycles FPU1 issue queue full 1 Group 20 pm_isu_queues1
PM_FXLS0_FULL_CYC_GRP20 Cycles FXU0/LS0 queue full 2 Group 20 pm_isu_queues1
PM_FXLS1_FULL_CYC_GRP20 Cycles FXU1/LS1 queue full 3 Group 20 pm_isu_queues1
PM_CYC_GRP20 Processor cycles 4 Group 20 pm_isu_queues1
PM_INST_CMPL_GRP20 Instructions completed 5 Group 20 pm_isu_queues1
PM_LSU_LRQ_FULL_CYC_GRP20 Cycles LRQ full 6 Group 20 pm_isu_queues1
PM_LSU_SRQ_FULL_CYC_GRP20 Cycles SRQ full 7 Group 20 pm_isu_queues1
PM_INST_DISP_GRP21 Instructions dispatched 0 Group 21 pm_isu_flow
PM_CYC_GRP21 Processor cycles 1 Group 21 pm_isu_flow
PM_FXU0_FIN_GRP21 FXU0 produced a result 2 Group 21 pm_isu_flow
PM_FXU1_FIN_GRP21 FXU1 produced a result 3 Group 21 pm_isu_flow
PM_GRP_DISP_VALID_GRP21 Group dispatch valid 4 Group 21 pm_isu_flow
PM_GRP_DISP_REJECT_GRP21 Group dispatch rejected 5 Group 21 pm_isu_flow
PM_INST_CMPL_GRP21 Instructions completed 6 Group 21 pm_isu_flow
PM_CYC_GRP21 Processor cycles 7 Group 21 pm_isu_flow
PM_GCT_EMPTY_CYC_GRP22 Cycles GCT empty 0 Group 22 pm_isu_work
PM_WORK_HELD_GRP22 Work held 1 Group 22 pm_isu_work
PM_STOP_COMPLETION_GRP22 Completion stopped 2 Group 22 pm_isu_work
PM_EE_OFF_EXT_INT_GRP22 Cycles MSR(EE) bit off and external interrupt pending 3 Group 22 pm_isu_work
PM_CYC_GRP22 Processor cycles 4 Group 22 pm_isu_work
PM_INST_CMPL_GRP22 Instructions completed 5 Group 22 pm_isu_work
PM_EE_OFF_GRP22 Cycles MSR(EE) bit off 6 Group 22 pm_isu_work
PM_EXT_INT_GRP22 External interrupts 7 Group 22 pm_isu_work
PM_SNOOP_TLBIE_GRP23 Snoop TLBIE 0 Group 23 pm_serialize
PM_STCX_FAIL_GRP23 STCX failed 1 Group 23 pm_serialize
PM_STCX_PASS_GRP23 Stcx passes 2 Group 23 pm_serialize
PM_CYC_GRP23 Processor cycles 3 Group 23 pm_serialize
PM_1PLUS_PPC_CMPL_GRP23 One or more PPC instruction completed 4 Group 23 pm_serialize
PM_INST_CMPL_GRP23 Instructions completed 5 Group 23 pm_serialize
PM_LARX_LSU0_GRP23 Larx executed on LSU0 6 Group 23 pm_serialize
PM_LARX_LSU1_GRP23 Larx executed on LSU1 7 Group 23 pm_serialize
PM_LSU_SRQ_S0_VALID_GRP24 SRQ slot 0 valid 0 Group 24 pm_lsubusy
PM_LSU_SRQ_S0_ALLOC_GRP24 SRQ slot 0 allocated 1 Group 24 pm_lsubusy
PM_LSU0_BUSY_GRP24 LSU0 busy 2 Group 24 pm_lsubusy
PM_LSU1_BUSY_GRP24 LSU1 busy 3 Group 24 pm_lsubusy
PM_LSU_LRQ_S0_VALID_GRP24 LRQ slot 0 valid 4 Group 24 pm_lsubusy
PM_LSU_LRQ_S0_ALLOC_GRP24 LRQ slot 0 allocated 5 Group 24 pm_lsubusy
PM_INST_CMPL_GRP24 Instructions completed 6 Group 24 pm_lsubusy
PM_CYC_GRP24 Processor cycles 7 Group 24 pm_lsubusy
PM_INST_CMPL_GRP25 Instructions completed 0 Group 25 pm_lsource2
PM_L1_DCACHE_RELOAD_VALID_GRP25 L1 reload data source valid 1 Group 25 pm_lsource2
PM_CYC_GRP25 Processor cycles 2 Group 25 pm_lsource2
PM_DATA_FROM_L2_GRP25 Data loaded from L2 3 Group 25 pm_lsource2
PM_DATA_FROM_L25_SHR_GRP25 Data loaded from L2.5 shared 4 Group 25 pm_lsource2
PM_DATA_FROM_L275_SHR_GRP25 Data loaded from L2.75 shared 5 Group 25 pm_lsource2
PM_DATA_FROM_L275_MOD_GRP25 Data loaded from L2.75 modified 6 Group 25 pm_lsource2
PM_DATA_FROM_L25_MOD_GRP25 Data loaded from L2.5 modified 7 Group 25 pm_lsource2
PM_DATA_FROM_L3_GRP26 Data loaded from L3 0 Group 26 pm_lsource3
PM_DATA_FROM_MEM_GRP26 Data loaded from memory 1 Group 26 pm_lsource3
PM_DATA_FROM_L35_GRP26 Data loaded from L3.5 2 Group 26 pm_lsource3
PM_DATA_FROM_L2_GRP26 Data loaded from L2 3 Group 26 pm_lsource3
PM_L1_DCACHE_RELOAD_VALID_GRP26 L1 reload data source valid 4 Group 26 pm_lsource3
PM_CYC_GRP26 Processor cycles 5 Group 26 pm_lsource3
PM_DATA_FROM_L275_MOD_GRP26 Data loaded from L2.75 modified 6 Group 26 pm_lsource3
PM_INST_CMPL_GRP26 Instructions completed 7 Group 26 pm_lsource3
PM_INST_CMPL_GRP27 Instructions completed 0 Group 27 pm_isource2
PM_CYC_GRP27 Processor cycles 1 Group 27 pm_isource2
PM_INST_FROM_L2_GRP27 Instructions fetched from L2 2 Group 27 pm_isource2
PM_INST_FROM_L35_GRP27 Instructions fetched from L3.5 3 Group 27 pm_isource2
PM_INST_FROM_L3_GRP27 Instruction fetched from L3 4 Group 27 pm_isource2
PM_INST_FROM_L1_GRP27 Instruction fetched from L1 5 Group 27 pm_isource2
PM_INST_FROM_PREF_GRP27 Instructions fetched from prefetch 6 Group 27 pm_isource2
PM_0INST_FETCH_GRP27 No instructions fetched 7 Group 27 pm_isource2
PM_INST_FROM_MEM_GRP28 Instruction fetched from memory 0 Group 28 pm_isource3
PM_INST_FROM_L25_L275_GRP28 Instruction fetched from L2.5/L2.75 1 Group 28 pm_isource3
PM_INST_FROM_L2_GRP28 Instructions fetched from L2 2 Group 28 pm_isource3
PM_INST_FROM_L35_GRP28 Instructions fetched from L3.5 3 Group 28 pm_isource3
PM_INST_FROM_L3_GRP28 Instruction fetched from L3 4 Group 28 pm_isource3
PM_INST_FROM_L1_GRP28 Instruction fetched from L1 5 Group 28 pm_isource3
PM_CYC_GRP28 Processor cycles 6 Group 28 pm_isource3
PM_INST_CMPL_GRP28 Instructions completed 7 Group 28 pm_isource3
PM_FPU0_FDIV_GRP29 FPU0 executed FDIV instruction 0 Group 29 pm_fpu3
PM_FPU1_FDIV_GRP29 FPU1 executed FDIV instruction 1 Group 29 pm_fpu3
PM_FPU0_FRSP_FCONV_GRP29 FPU0 executed FRSP or FCONV instructions 2 Group 29 pm_fpu3
PM_FPU1_FRSP_FCONV_GRP29 FPU1 executed FRSP or FCONV instructions 3 Group 29 pm_fpu3
PM_FPU0_FMA_GRP29 FPU0 executed multiply-add instruction 4 Group 29 pm_fpu3
PM_FPU1_FMA_GRP29 FPU1 executed multiply-add instruction 5 Group 29 pm_fpu3
PM_INST_CMPL_GRP29 Instructions completed 6 Group 29 pm_fpu3
PM_CYC_GRP29 Processor cycles 7 Group 29 pm_fpu3
PM_FPU0_FSQRT_GRP30 FPU0 executed FSQRT instruction 0 Group 30 pm_fpu4
PM_FPU1_FSQRT_GRP30 FPU1 executed FSQRT instruction 1 Group 30 pm_fpu4
PM_FPU0_FIN_GRP30 FPU0 produced a result 2 Group 30 pm_fpu4
PM_FPU1_FIN_GRP30 FPU1 produced a result 3 Group 30 pm_fpu4
PM_FPU0_ALL_GRP30 FPU0 executed add, mult, sub, cmp or sel instruction 4 Group 30 pm_fpu4
PM_FPU1_ALL_GRP30 FPU1 executed add, mult, sub, cmp or sel instruction 5 Group 30 pm_fpu4
PM_INST_CMPL_GRP30 Instructions completed 6 Group 30 pm_fpu4
PM_CYC_GRP30 Processor cycles 7 Group 30 pm_fpu4
PM_FPU0_DENORM_GRP31 FPU0 received denormalized data 0 Group 31 pm_fpu5
PM_FPU1_DENORM_GRP31 FPU1 received denormalized data 1 Group 31 pm_fpu5
PM_FPU0_FMOV_FEST_GRP31 FPU0 executed FMOV or FEST instructions 2 Group 31 pm_fpu5
PM_FPU1_FMOV_FEST_GRP31 FPU1 executing FMOV or FEST instructions 3 Group 31 pm_fpu5
PM_CYC_GRP31 Processor cycles 4 Group 31 pm_fpu5
PM_INST_CMPL_GRP31 Instructions completed 5 Group 31 pm_fpu5
PM_FPU0_FEST_GRP31 FPU0 executed FEST instruction 6 Group 31 pm_fpu5
PM_FPU1_FEST_GRP31 FPU1 executed FEST instruction 7 Group 31 pm_fpu5
PM_FPU0_SINGLE_GRP32 FPU0 executed single precision instruction 0 Group 32 pm_fpu6
PM_FPU1_SINGLE_GRP32 FPU1 executed single precision instruction 1 Group 32 pm_fpu6
PM_LSU0_LDF_GRP32 LSU0 executed Floating Point load instruction 2 Group 32 pm_fpu6
PM_LSU1_LDF_GRP32 LSU1 executed Floating Point load instruction 3 Group 32 pm_fpu6
PM_FPU0_STF_GRP32 FPU0 executed store instruction 4 Group 32 pm_fpu6
PM_FPU1_STF_GRP32 FPU1 executed store instruction 5 Group 32 pm_fpu6
PM_CYC_GRP32 Processor cycles 6 Group 32 pm_fpu6
PM_INST_CMPL_GRP32 Instructions completed 7 Group 32 pm_fpu6
PM_FPU0_STALL3_GRP33 FPU0 stalled in pipe3 0 Group 33 pm_fpu7
PM_FPU1_STALL3_GRP33 FPU1 stalled in pipe3 1 Group 33 pm_fpu7
PM_FPU0_FIN_GRP33 FPU0 produced a result 2 Group 33 pm_fpu7
PM_FPU1_FIN_GRP33 FPU1 produced a result 3 Group 33 pm_fpu7
PM_CYC_GRP33 Processor cycles 4 Group 33 pm_fpu7
PM_INST_CMPL_GRP33 Instructions completed 5 Group 33 pm_fpu7
PM_CYC_GRP33 Processor cycles 6 Group 33 pm_fpu7
PM_FPU0_FPSCR_GRP33 FPU0 executed FPSCR instruction 7 Group 33 pm_fpu7
PM_INST_CMPL_GRP34 Instructions completed 0 Group 34 pm_fxu
PM_CYC_GRP34 Processor cycles 1 Group 34 pm_fxu
PM_FXU_FIN_GRP34 FXU produced a result 2 Group 34 pm_fxu
PM_FXU1_BUSY_FXU0_IDLE_GRP34 FXU1 busy FXU0 idle 3 Group 34 pm_fxu
PM_FXU_IDLE_GRP34 FXU idle 4 Group 34 pm_fxu
PM_FXU_BUSY_GRP34 FXU busy 5 Group 34 pm_fxu
PM_FXU0_BUSY_FXU1_IDLE_GRP34 FXU0 busy FXU1 idle 6 Group 34 pm_fxu
PM_FXLS_FULL_CYC_GRP34 Cycles FXLS queue is full 7 Group 34 pm_fxu
PM_LSU_LMQ_LHR_MERGE_GRP35 LMQ LHR merges 0 Group 35 pm_lsu_lmq
PM_LSU_LMQ_FULL_CYC_GRP35 Cycles LMQ full 1 Group 35 pm_lsu_lmq
PM_LSU_LMQ_S0_ALLOC_GRP35 LMQ slot 0 allocated 2 Group 35 pm_lsu_lmq
PM_LSU_LMQ_S0_VALID_GRP35 LMQ slot 0 valid 3 Group 35 pm_lsu_lmq
PM_CYC_GRP35 Processor cycles 4 Group 35 pm_lsu_lmq
PM_INST_CMPL_GRP35 Instructions completed 5 Group 35 pm_lsu_lmq
PM_LSU_SRQ_SYNC_CYC_GRP35 SRQ sync duration 6 Group 35 pm_lsu_lmq
PM_DATA_TABLEWALK_CYC_GRP35 Cycles doing data tablewalks 7 Group 35 pm_lsu_lmq
PM_LSU0_FLUSH_LRQ_GRP36 LSU0 LRQ flushes 0 Group 36 pm_lsu_flush
PM_LSU1_FLUSH_LRQ_GRP36 LSU1 LRQ flushes 1 Group 36 pm_lsu_flush
PM_CYC_GRP36 Processor cycles 2 Group 36 pm_lsu_flush
PM_CYC_GRP36 Processor cycles 3 Group 36 pm_lsu_flush
PM_LSU0_FLUSH_SRQ_GRP36 LSU0 SRQ flushes 4 Group 36 pm_lsu_flush
PM_LSU1_FLUSH_SRQ_GRP36 LSU1 SRQ flushes 5 Group 36 pm_lsu_flush
PM_INST_CMPL_GRP36 Instructions completed 6 Group 36 pm_lsu_flush
PM_CYC_GRP36 Processor cycles 7 Group 36 pm_lsu_flush
PM_LSU0_FLUSH_ULD_GRP37 LSU0 unaligned load flushes 0 Group 37 pm_lsu_load1
PM_LSU1_FLUSH_ULD_GRP37 LSU1 unaligned load flushes 1 Group 37 pm_lsu_load1
PM_LD_REF_L1_LSU0_GRP37 LSU0 L1 D cache load references 2 Group 37 pm_lsu_load1
PM_LD_REF_L1_LSU1_GRP37 LSU1 L1 D cache load references 3 Group 37 pm_lsu_load1
PM_CYC_GRP37 Processor cycles 4 Group 37 pm_lsu_load1
PM_INST_CMPL_GRP37 Instructions completed 5 Group 37 pm_lsu_load1
PM_LD_MISS_L1_LSU0_GRP37 LSU0 L1 D cache load misses 6 Group 37 pm_lsu_load1
PM_LD_MISS_L1_LSU1_GRP37 LSU1 L1 D cache load misses 7 Group 37 pm_lsu_load1
PM_LSU0_FLUSH_UST_GRP38 LSU0 unaligned store flushes 0 Group 38 pm_lsu_store1
PM_LSU1_FLUSH_UST_GRP38 LSU1 unaligned store flushes 1 Group 38 pm_lsu_store1
PM_ST_REF_L1_LSU0_GRP38 LSU0 L1 D cache store references 2 Group 38 pm_lsu_store1
PM_ST_REF_L1_LSU1_GRP38 LSU1 L1 D cache store references 3 Group 38 pm_lsu_store1
PM_CYC_GRP38 Processor cycles 4 Group 38 pm_lsu_store1
PM_INST_CMPL_GRP38 Instructions completed 5 Group 38 pm_lsu_store1
PM_ST_MISS_L1_GRP38 L1 D cache store misses 6 Group 38 pm_lsu_store1
PM_DC_INV_L2_GRP38 L1 D cache entries invalidated from L2 7 Group 38 pm_lsu_store1
PM_LSU0_SRQ_STFWD_GRP39 LSU0 SRQ store forwarded 0 Group 39 pm_lsu_store2
PM_LSU1_SRQ_STFWD_GRP39 LSU1 SRQ store forwarded 1 Group 39 pm_lsu_store2
PM_ST_REF_L1_LSU0_GRP39 LSU0 L1 D cache store references 2 Group 39 pm_lsu_store2
PM_ST_REF_L1_LSU1_GRP39 LSU1 L1 D cache store references 3 Group 39 pm_lsu_store2
PM_ST_MISS_L1_GRP39 L1 D cache store misses 4 Group 39 pm_lsu_store2
PM_CYC_GRP39 Processor cycles 5 Group 39 pm_lsu_store2
PM_INST_CMPL_GRP39 Instructions completed 6 Group 39 pm_lsu_store2
PM_CYC_GRP39 Processor cycles 7 Group 39 pm_lsu_store2
PM_LSU0_DERAT_MISS_GRP40 LSU0 DERAT misses 0 Group 40 pm_lsu7
PM_LSU1_DERAT_MISS_GRP40 LSU1 DERAT misses 1 Group 40 pm_lsu7
PM_CYC_GRP40 Processor cycles 2 Group 40 pm_lsu7
PM_CYC_GRP40 Processor cycles 3 Group 40 pm_lsu7
PM_L1_DCACHE_RELOAD_VALID_GRP40 L1 reload data source valid 4 Group 40 pm_lsu7
PM_CYC_GRP40 Processor cycles 5 Group 40 pm_lsu7
PM_INST_CMPL_GRP40 Instructions completed 6 Group 40 pm_lsu7
PM_CYC_GRP40 Processor cycles 7 Group 40 pm_lsu7
PM_DC_PREF_STREAM_ALLOC_GRP41 D cache new prefetch stream allocated 0 Group 41 pm_dpfetch
PM_DC_PREF_L2_CLONE_L3_GRP41 L2 prefetch cloned with L3 1 Group 41 pm_dpfetch
PM_L2_PREF_GRP41 L2 cache prefetches 2 Group 41 pm_dpfetch
PM_L1_PREF_GRP41 L1 cache data prefetches 3 Group 41 pm_dpfetch
PM_CYC_GRP41 Processor cycles 4 Group 41 pm_dpfetch
PM_INST_CMPL_GRP41 Instructions completed 5 Group 41 pm_dpfetch
PM_CYC_GRP41 Processor cycles 6 Group 41 pm_dpfetch
PM_DC_PREF_OUT_STREAMS_GRP41 Out of prefetch streams 7 Group 41 pm_dpfetch
PM_GCT_EMPTY_CYC_GRP42 Cycles GCT empty 0 Group 42 pm_misc
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP42 Cycles LMQ and SRQ empty 1 Group 42 pm_misc
PM_HV_CYC_GRP42 Hypervisor Cycles 2 Group 42 pm_misc
PM_CYC_GRP42 Processor cycles 3 Group 42 pm_misc
PM_1PLUS_PPC_CMPL_GRP42 One or more PPC instruction completed 4 Group 42 pm_misc
PM_INST_CMPL_GRP42 Instructions completed 5 Group 42 pm_misc
PM_GRP_CMPL_GRP42 Group completed 6 Group 42 pm_misc
PM_TB_BIT_TRANS_GRP42 Time Base bit transition 7 Group 42 pm_misc
PM_MRK_LD_MISS_L1_GRP43 Marked L1 D cache load misses 0 Group 43 pm_mark1
PM_THRESH_TIMEO_GRP43 Threshold timeout 1 Group 43 pm_mark1
PM_CYC_GRP43 Processor cycles 2 Group 43 pm_mark1
PM_MRK_GRP_CMPL_GRP43 Marked group completed 3 Group 43 pm_mark1
PM_GRP_MRK_GRP43 Group marked in IDU 4 Group 43 pm_mark1
PM_MRK_GRP_ISSUED_GRP43 Marked group issued 5 Group 43 pm_mark1
PM_MRK_INST_FIN_GRP43 Marked instruction finished 6 Group 43 pm_mark1
PM_INST_CMPL_GRP43 Instructions completed 7 Group 43 pm_mark1
PM_MRK_GRP_DISP_GRP44 Marked group dispatched 0 Group 44 pm_mark2
PM_MRK_BRU_FIN_GRP44 Marked instruction BRU processing finished 1 Group 44 pm_mark2
PM_CYC_GRP44 Processor cycles 2 Group 44 pm_mark2
PM_MRK_CRU_FIN_GRP44 Marked instruction CRU processing finished 3 Group 44 pm_mark2
PM_GRP_MRK_GRP44 Group marked in IDU 4 Group 44 pm_mark2
PM_MRK_FXU_FIN_GRP44 Marked instruction FXU processing finished 5 Group 44 pm_mark2
PM_MRK_FPU_FIN_GRP44 Marked instruction FPU processing finished 6 Group 44 pm_mark2
PM_MRK_LSU_FIN_GRP44 Marked instruction LSU processing finished 7 Group 44 pm_mark2
PM_MRK_ST_CMPL_GRP45 Marked store instruction completed 0 Group 45 pm_mark3
PM_CYC_GRP45 Processor cycles 1 Group 45 pm_mark3
PM_MRK_ST_CMPL_INT_GRP45 Marked store completed with intervention 2 Group 45 pm_mark3
PM_MRK_GRP_CMPL_GRP45 Marked group completed 3 Group 45 pm_mark3
PM_MRK_GRP_TIMEO_GRP45 Marked group completion timeout 4 Group 45 pm_mark3
PM_MRK_ST_GPS_GRP45 Marked store sent to GPS 5 Group 45 pm_mark3
PM_MRK_LSU_SRQ_INST_VALID_GRP45 Marked instruction valid in SRQ 6 Group 45 pm_mark3
PM_INST_CMPL_GRP45 Instructions completed 7 Group 45 pm_mark3
PM_MRK_LD_MISS_L1_GRP46 Marked L1 D cache load misses 0 Group 46 pm_mark4
PM_CYC_GRP46 Processor cycles 1 Group 46 pm_mark4
PM_MRK_LSU_FLUSH_LRQ_GRP46 Marked LRQ flushes 2 Group 46 pm_mark4
PM_MRK_LSU_FLUSH_SRQ_GRP46 Marked SRQ flushes 3 Group 46 pm_mark4
PM_MRK_GRP_TIMEO_GRP46 Marked group completion timeout 4 Group 46 pm_mark4
PM_MRK_GRP_ISSUED_GRP46 Marked group issued 5 Group 46 pm_mark4
PM_INST_CMPL_GRP46 Instructions completed 6 Group 46 pm_mark4
PM_MRK_LSU_FLUSH_ULD_GRP46 Marked unaligned load flushes 7 Group 46 pm_mark4
PM_MRK_DATA_FROM_L3_GRP47 Marked data loaded from L3 0 Group 47 pm_mark_lsource
PM_MRK_DATA_FROM_MEM_GRP47 Marked data loaded from memory 1 Group 47 pm_mark_lsource
PM_MRK_DATA_FROM_L35_GRP47 Marked data loaded from L3.5 2 Group 47 pm_mark_lsource
PM_MRK_DATA_FROM_L2_GRP47 Marked data loaded from L2 3 Group 47 pm_mark_lsource
PM_MRK_DATA_FROM_L25_SHR_GRP47 Marked data loaded from L2.5 shared 4 Group 47 pm_mark_lsource
PM_MRK_DATA_FROM_L275_SHR_GRP47 Marked data loaded from L2.75 shared 5 Group 47 pm_mark_lsource
PM_MRK_DATA_FROM_L275_MOD_GRP47 Marked data loaded from L2.75 modified 6 Group 47 pm_mark_lsource
PM_MRK_DATA_FROM_L25_MOD_GRP47 Marked data loaded from L2.5 modified 7 Group 47 pm_mark_lsource
PM_INST_CMPL_GRP48 Instructions completed 0 Group 48 pm_mark_lsource2
PM_CYC_GRP48 Processor cycles 1 Group 48 pm_mark_lsource2
PM_MRK_L1_RELOAD_VALID_GRP48 Marked L1 reload data source valid 2 Group 48 pm_mark_lsource2
PM_MRK_DATA_FROM_L2_GRP48 Marked data loaded from L2 3 Group 48 pm_mark_lsource2
PM_MRK_DATA_FROM_L25_SHR_GRP48 Marked data loaded from L2.5 shared 4 Group 48 pm_mark_lsource2
PM_MRK_DATA_FROM_L275_SHR_GRP48 Marked data loaded from L2.75 shared 5 Group 48 pm_mark_lsource2
PM_MRK_DATA_FROM_L275_MOD_GRP48 Marked data loaded from L2.75 modified 6 Group 48 pm_mark_lsource2
PM_MRK_DATA_FROM_L25_MOD_GRP48 Marked data loaded from L2.5 modified 7 Group 48 pm_mark_lsource2
PM_MRK_DATA_FROM_L3_GRP49 Marked data loaded from L3 0 Group 49 pm_mark_lsource3
PM_MRK_DATA_FROM_MEM_GRP49 Marked data loaded from memory 1 Group 49 pm_mark_lsource3
PM_MRK_DATA_FROM_L35_GRP49 Marked data loaded from L3.5 2 Group 49 pm_mark_lsource3
PM_MRK_DATA_FROM_L2_GRP49 Marked data loaded from L2 3 Group 49 pm_mark_lsource3
PM_CYC_GRP49 Processor cycles 4 Group 49 pm_mark_lsource3
PM_INST_CMPL_GRP49 Instructions completed 5 Group 49 pm_mark_lsource3
PM_MRK_DATA_FROM_L275_MOD_GRP49 Marked data loaded from L2.75 modified 6 Group 49 pm_mark_lsource3
PM_MRK_L1_RELOAD_VALID_GRP49 Marked L1 reload data source valid 7 Group 49 pm_mark_lsource3
PM_MRK_ST_MISS_L1_GRP50 Marked L1 D cache store misses 0 Group 50 pm_lsu_mark1
PM_MRK_IMR_RELOAD_GRP50 Marked IMR reloaded 1 Group 50 pm_lsu_mark1
PM_MRK_LSU0_FLUSH_ULD_GRP50 LSU0 marked unaligned load flushes 2 Group 50 pm_lsu_mark1
PM_MRK_LSU1_FLUSH_ULD_GRP50 LSU1 marked unaligned load flushes 3 Group 50 pm_lsu_mark1
PM_CYC_GRP50 Processor cycles 4 Group 50 pm_lsu_mark1
PM_INST_CMPL_GRP50 Instructions completed 5 Group 50 pm_lsu_mark1
PM_MRK_LSU0_FLUSH_UST_GRP50 LSU0 marked unaligned store flushes 6 Group 50 pm_lsu_mark1
PM_MRK_LSU1_FLUSH_UST_GRP50 LSU1 marked unaligned store flushes 7 Group 50 pm_lsu_mark1
PM_MRK_LD_MISS_L1_LSU0_GRP51 LSU0 L1 D cache load misses 0 Group 51 pm_lsu_mark2
PM_MRK_LD_MISS_L1_LSU1_GRP51 LSU1 L1 D cache load misses 1 Group 51 pm_lsu_mark2
PM_MRK_LSU0_FLUSH_LRQ_GRP51 LSU0 marked LRQ flushes 2 Group 51 pm_lsu_mark2
PM_MRK_LSU1_FLUSH_LRQ_GRP51 LSU1 marked LRQ flushes 3 Group 51 pm_lsu_mark2
PM_CYC_GRP51 Processor cycles 4 Group 51 pm_lsu_mark2
PM_INST_CMPL_GRP51 Instructions completed 5 Group 51 pm_lsu_mark2
PM_MRK_LSU0_FLUSH_SRQ_GRP51 LSU0 marked SRQ flushes 6 Group 51 pm_lsu_mark2
PM_MRK_LSU1_FLUSH_SRQ_GRP51 LSU1 marked SRQ flushes 7 Group 51 pm_lsu_mark2
PM_MRK_STCX_FAIL_GRP52 Marked STCX failed 0 Group 52 pm_lsu_mark3
PM_CYC_GRP52 Processor cycles 1 Group 52 pm_lsu_mark3
PM_MRK_LSU0_INST_FIN_GRP52 LSU0 finished a marked instruction 2 Group 52 pm_lsu_mark3
PM_MRK_LSU1_INST_FIN_GRP52 LSU1 finished a marked instruction 3 Group 52 pm_lsu_mark3
PM_CYC_GRP52 Processor cycles 4 Group 52 pm_lsu_mark3
PM_MRK_GRP_ISSUED_GRP52 Marked group issued 5 Group 52 pm_lsu_mark3
PM_MRK_INST_FIN_GRP52 Marked instruction finished 6 Group 52 pm_lsu_mark3
PM_INST_CMPL_GRP52 Instructions completed 7 Group 52 pm_lsu_mark3
PM_LSU_LMQ_LHR_MERGE_GRP53 LMQ LHR merges 0 Group 53 pm_threshold
PM_THRESH_TIMEO_GRP53 Threshold timeout 1 Group 53 pm_threshold
PM_LSU_LMQ_S0_VALID_GRP53 LMQ slot 0 valid 2 Group 53 pm_threshold
PM_INST_CMPL_GRP53 Instructions completed 3 Group 53 pm_threshold
PM_CYC_GRP53 Processor cycles 4 Group 53 pm_threshold
PM_MRK_GRP_ISSUED_GRP53 Marked group issued 5 Group 53 pm_threshold
PM_GRP_CMPL_GRP53 Group completed 6 Group 53 pm_threshold
PM_LSU_LMQ_S0_ALLOC_GRP53 LMQ slot 0 allocated 7 Group 53 pm_threshold
PM_FPU_FDIV_GRP54 FPU executed FDIV instruction 0 Group 54 pm_pe_bench1
PM_FPU_FMA_GRP54 FPU executed multiply-add instruction 1 Group 54 pm_pe_bench1
PM_FXU_FIN_GRP54 FXU produced a result 2 Group 54 pm_pe_bench1
PM_FPU_FIN_GRP54 FPU produced a result 3 Group 54 pm_pe_bench1
PM_CYC_GRP54 Processor cycles 4 Group 54 pm_pe_bench1
PM_FPU_FSQRT_GRP54 FPU executed FSQRT instruction 5 Group 54 pm_pe_bench1
PM_INST_CMPL_GRP54 Instructions completed 6 Group 54 pm_pe_bench1
PM_FPU_FMOV_FEST_GRP54 FPU executing FMOV or FEST instructions 7 Group 54 pm_pe_bench1
PM_CYC_GRP55 Processor cycles 0 Group 55 pm_pe_bench2
PM_FPU_STALL3_GRP55 FPU stalled in pipe3 1 Group 55 pm_pe_bench2
PM_FPU0_FIN_GRP55 FPU0 produced a result 2 Group 55 pm_pe_bench2
PM_INST_CMPL_GRP55 Instructions completed 3 Group 55 pm_pe_bench2
PM_FPU_FULL_CYC_GRP55 Cycles FPU issue queue full 4 Group 55 pm_pe_bench2
PM_FPU_STF_GRP55 FPU executed store instruction 5 Group 55 pm_pe_bench2
PM_FPU1_FIN_GRP55 FPU1 produced a result 6 Group 55 pm_pe_bench2
PM_LSU_LDF_GRP55 LSU executed Floating Point load instruction 7 Group 55 pm_pe_bench2
PM_INST_CMPL_GRP56 Instructions completed 0 Group 56 pm_pe_bench3
PM_BIQ_IDU_FULL_CYC_GRP56 Cycles BIQ or IDU full 1 Group 56 pm_pe_bench3
PM_BR_ISSUED_GRP56 Branches issued 2 Group 56 pm_pe_bench3
PM_BR_MPRED_CR_GRP56 Branch mispredictions due CR bit setting 3 Group 56 pm_pe_bench3
PM_BRQ_FULL_CYC_GRP56 Cycles branch queue full 4 Group 56 pm_pe_bench3
PM_CYC_GRP56 Processor cycles 5 Group 56 pm_pe_bench3
PM_BR_MPRED_TA_GRP56 Branch mispredictions due to target address 6 Group 56 pm_pe_bench3
PM_L1_WRITE_CYC_GRP56 Cycles writing to instruction L1 7 Group 56 pm_pe_bench3
PM_DTLB_MISS_GRP57 Data TLB misses 0 Group 57 pm_pe_bench4
PM_ITLB_MISS_GRP57 Instruction TLB misses 1 Group 57 pm_pe_bench4
PM_LD_MISS_L1_GRP57 L1 D cache load misses 2 Group 57 pm_pe_bench4
PM_ST_MISS_L1_GRP57 L1 D cache store misses 3 Group 57 pm_pe_bench4
PM_CYC_GRP57 Processor cycles 4 Group 57 pm_pe_bench4
PM_INST_CMPL_GRP57 Instructions completed 5 Group 57 pm_pe_bench4
PM_ST_REF_L1_GRP57 L1 D cache store references 6 Group 57 pm_pe_bench4
PM_LD_REF_L1_GRP57 L1 D cache load references 7 Group 57 pm_pe_bench4
PM_INST_CMPL_GRP58 Instructions completed 0 Group 58 pm_pe_bench5
PM_CYC_GRP58 Processor cycles 1 Group 58 pm_pe_bench5
PM_DATA_FROM_L35_GRP58 Data loaded from L3.5 2 Group 58 pm_pe_bench5
PM_DATA_FROM_L2_GRP58 Data loaded from L2 3 Group 58 pm_pe_bench5
PM_DATA_FROM_L25_SHR_GRP58 Data loaded from L2.5 shared 4 Group 58 pm_pe_bench5
PM_DATA_FROM_L275_SHR_GRP58 Data loaded from L2.75 shared 5 Group 58 pm_pe_bench5
PM_DATA_FROM_L275_MOD_GRP58 Data loaded from L2.75 modified 6 Group 58 pm_pe_bench5
PM_DATA_FROM_L25_MOD_GRP58 Data loaded from L2.5 modified 7 Group 58 pm_pe_bench5
PM_DATA_FROM_L3_GRP59 Data loaded from L3 0 Group 59 pm_pe_bench6
PM_DATA_FROM_MEM_GRP59 Data loaded from memory 1 Group 59 pm_pe_bench6
PM_DATA_FROM_L35_GRP59 Data loaded from L3.5 2 Group 59 pm_pe_bench6
PM_DATA_FROM_L2_GRP59 Data loaded from L2 3 Group 59 pm_pe_bench6
PM_DATA_FROM_L25_SHR_GRP59 Data loaded from L2.5 shared 4 Group 59 pm_pe_bench6
PM_CYC_GRP59 Processor cycles 5 Group 59 pm_pe_bench6
PM_INST_CMPL_GRP59 Instructions completed 6 Group 59 pm_pe_bench6
PM_DATA_FROM_L25_MOD_GRP59 Data loaded from L2.5 modified 7 Group 59 pm_pe_bench6
PM_DTLB_MISS_GRP60 Data TLB misses 0 Group 60 pm_hpmcount1
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP60 Cycles LMQ and SRQ empty 1 Group 60 pm_hpmcount1
PM_LD_MISS_L1_GRP60 L1 D cache load misses 2 Group 60 pm_hpmcount1
PM_ST_MISS_L1_GRP60 L1 D cache store misses 3 Group 60 pm_hpmcount1
PM_CYC_GRP60 Processor cycles 4 Group 60 pm_hpmcount1
PM_INST_CMPL_GRP60 Instructions completed 5 Group 60 pm_hpmcount1
PM_ST_REF_L1_GRP60 L1 D cache store references 6 Group 60 pm_hpmcount1
PM_LD_REF_L1_GRP60 L1 D cache load references 7 Group 60 pm_hpmcount1
PM_FPU_FDIV_GRP61 FPU executed FDIV instruction 0 Group 61 pm_hpmcount2
PM_FPU_FMA_GRP61 FPU executed multiply-add instruction 1 Group 61 pm_hpmcount2
PM_FPU0_FIN_GRP61 FPU0 produced a result 2 Group 61 pm_hpmcount2
PM_FPU1_FIN_GRP61 FPU1 produced a result 3 Group 61 pm_hpmcount2
PM_CYC_GRP61 Processor cycles 4 Group 61 pm_hpmcount2
PM_FPU_STF_GRP61 FPU executed store instruction 5 Group 61 pm_hpmcount2
PM_INST_CMPL_GRP61 Instructions completed 6 Group 61 pm_hpmcount2
PM_LSU_LDF_GRP61 LSU executed Floating Point load instruction 7 Group 61 pm_hpmcount2
PM_INST_CMPL_GRP62 Instructions completed 0 Group 62 pm_l1andbr
PM_CYC_GRP62 Processor cycles 1 Group 62 pm_l1andbr
PM_LD_MISS_L1_GRP62 L1 D cache load misses 2 Group 62 pm_l1andbr
PM_BR_ISSUED_GRP62 Branches issued 3 Group 62 pm_l1andbr
PM_ST_MISS_L1_GRP62 L1 D cache store misses 4 Group 62 pm_l1andbr
PM_CYC_GRP62 Processor cycles 5 Group 62 pm_l1andbr
PM_BR_MPRED_CR_GRP62 Branch mispredictions due CR bit setting 6 Group 62 pm_l1andbr
PM_BR_MPRED_TA_GRP62 Branch mispredictions due to target address 7 Group 62 pm_l1andbr
PM_INST_CMPL_GRP63 Instructions completed 0 Group 63 pm_imix
PM_CYC_GRP63 Processor cycles 1 Group 63 pm_imix
PM_LD_MISS_L1_GRP63 L1 D cache load misses 2 Group 63 pm_imix
PM_BR_ISSUED_GRP63 Branches issued 3 Group 63 pm_imix
PM_CYC_GRP63 Processor cycles 4 Group 63 pm_imix
PM_ST_MISS_L1_GRP63 L1 D cache store misses 5 Group 63 pm_imix
PM_ST_REF_L1_GRP63 L1 D cache store references 6 Group 63 pm_imix
PM_LD_REF_L1_GRP63 L1 D cache load references 7 Group 63 pm_imix
Bottlenecks occur in surprising places, so don't try to second guess and put in a speed hack until you've proven that's where the bottleneck is. - Rob Pike
2014/09/12