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ppc64 POWER5++ events

This is a list of all ppc64 POWER5++'s performance counter event types.

NameDescriptionCounters usableGroup
CYCLES Processor Cycles 1
PM_RUN_CYC_GRP1 Run cycles 0 Group 1 pm_utilization
PM_INST_CMPL_GRP1 Instructions completed 1 Group 1 pm_utilization
PM_INST_DISP_GRP1 Instructions dispatched 2 Group 1 pm_utilization
PM_CYC_GRP1 Processor cycles 3 Group 1 pm_utilization
PM_1PLUS_PPC_CMPL_GRP2 One or more PPC instruction completed 0 Group 2 pm_completion
PM_GCT_EMPTY_CYC_GRP2 Cycles GCT empty 1 Group 2 pm_completion
PM_GRP_CMPL_GRP2 Group completed 2 Group 2 pm_completion
PM_CYC_GRP2 Processor cycles 3 Group 2 pm_completion
PM_GRP_DISP_VALID_GRP3 Group dispatch valid 0 Group 3 pm_group_dispatch
PM_GRP_DISP_REJECT_GRP3 Group dispatch rejected 1 Group 3 pm_group_dispatch
PM_GRP_DISP_BLK_SB_CYC_GRP3 Cycles group dispatch blocked by scoreboard 2 Group 3 pm_group_dispatch
PM_INST_DISP_GRP3 Instructions dispatched 3 Group 3 pm_group_dispatch
PM_0INST_CLB_CYC_GRP4 Cycles no instructions in CLB 0 Group 4 pm_clb1
PM_2INST_CLB_CYC_GRP4 Cycles 2 instructions in CLB 1 Group 4 pm_clb1
PM_CLB_EMPTY_CYC_GRP4 Cycles CLB empty 2 Group 4 pm_clb1
PM_MRK_DATA_FROM_L35_MOD_CYC_GRP4 Marked load latency from L3.5 modified 3 Group 4 pm_clb1
PM_5INST_CLB_CYC_GRP5 Cycles 5 instructions in CLB 0 Group 5 pm_clb2
PM_6INST_CLB_CYC_GRP5 Cycles 6 instructions in CLB 1 Group 5 pm_clb2
PM_MRK_LSU_SRQ_INST_VALID_GRP5 Marked instruction valid in SRQ 2 Group 5 pm_clb2
PM_IOPS_CMPL_GRP5 Internal operations completed 3 Group 5 pm_clb2
PM_GCT_NOSLOT_CYC_GRP6 Cycles no GCT slot allocated 0 Group 6 pm_gct_empty
PM_GCT_NOSLOT_IC_MISS_GRP6 No slot in GCT caused by I cache miss 1 Group 6 pm_gct_empty
PM_GCT_NOSLOT_SRQ_FULL_GRP6 No slot in GCT caused by SRQ full 2 Group 6 pm_gct_empty
PM_GCT_NOSLOT_BR_MPRED_GRP6 No slot in GCT caused by branch mispredict 3 Group 6 pm_gct_empty
PM_GCT_USAGE_00to59_CYC_GRP7 Cycles GCT less than 60% full 0 Group 7 pm_gct_usage
PM_GCT_USAGE_60to79_CYC_GRP7 Cycles GCT 60-79% full 1 Group 7 pm_gct_usage
PM_GCT_USAGE_80to99_CYC_GRP7 Cycles GCT 80-99% full 2 Group 7 pm_gct_usage
PM_GCT_FULL_CYC_GRP7 Cycles GCT full 3 Group 7 pm_gct_usage
PM_LSU_LRQ_S0_ALLOC_GRP8 LRQ slot 0 allocated 0 Group 8 pm_lsu1
PM_LSU_LRQ_S0_VALID_GRP8 LRQ slot 0 valid 1 Group 8 pm_lsu1
PM_LSU_LMQ_S0_ALLOC_GRP8 LMQ slot 0 allocated 2 Group 8 pm_lsu1
PM_LSU_LMQ_S0_VALID_GRP8 LMQ slot 0 valid 3 Group 8 pm_lsu1
PM_LSU_SRQ_S0_ALLOC_GRP9 SRQ slot 0 allocated 0 Group 9 pm_lsu2
PM_LSU_SRQ_S0_VALID_GRP9 SRQ slot 0 valid 1 Group 9 pm_lsu2
PM_LSU_SRQ_SYNC_CYC_GRP9 SRQ sync duration 2 Group 9 pm_lsu2
PM_LSU_SRQ_FULL_CYC_GRP9 Cycles SRQ full 3 Group 9 pm_lsu2
PM_LSU_LMQ_LHR_MERGE_GRP10 LMQ LHR merges 0 Group 10 pm_lsu3
PM_LSU_SRQ_STFWD_GRP10 SRQ store forwarded 1 Group 10 pm_lsu3
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP10 Cycles LMQ and SRQ empty 2 Group 10 pm_lsu3
PM_LSU_SRQ_EMPTY_CYC_GRP10 Cycles SRQ empty 3 Group 10 pm_lsu3
PM_LSU_LMQ_FULL_CYC_GRP11 Cycles LMQ full 0 Group 11 pm_lsu4
PM_LSU_SRQ_FULL_CYC_GRP11 Cycles SRQ full 1 Group 11 pm_lsu4
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP11 Cycles LMQ and SRQ empty 2 Group 11 pm_lsu4
PM_LSU_SRQ_EMPTY_CYC_GRP11 Cycles SRQ empty 3 Group 11 pm_lsu4
PM_INST_FROM_L2MISS_GRP12 Instruction fetched missed L2 0 Group 12 pm_prefetch1
PM_INST_FETCH_CYC_GRP12 Cycles at least 1 instruction fetched 1 Group 12 pm_prefetch1
PM_DC_PREF_OUT_OF_STREAMS_GRP12 D cache out of prefetch streams 2 Group 12 pm_prefetch1
PM_DC_PREF_STREAM_ALLOC_GRP12 D cache new prefetch stream allocated 3 Group 12 pm_prefetch1
PM_IOPS_CMPL_GRP13 Internal operations completed 0 Group 13 pm_prefetch2
PM_CLB_FULL_CYC_GRP13 Cycles CLB full 1 Group 13 pm_prefetch2
PM_L1_PREF_GRP13 L1 cache data prefetches 2 Group 13 pm_prefetch2
PM_IC_PREF_INSTALL_GRP13 Instruction prefetched installed in prefetch buffer 3 Group 13 pm_prefetch2
PM_1INST_CLB_CYC_GRP14 Cycles 1 instruction in CLB 0 Group 14 pm_prefetch3
PM_LSU_BUSY_REJECT_GRP14 LSU busy due to reject 1 Group 14 pm_prefetch3
PM_L2_PREF_GRP14 L2 cache prefetches 2 Group 14 pm_prefetch3
PM_IOPS_CMPL_GRP14 Internal operations completed 3 Group 14 pm_prefetch3
PM_LSU0_REJECT_SRQ_GRP15 LSU0 SRQ lhs rejects 0 Group 15 pm_prefetch4
PM_LSU1_REJECT_SRQ_GRP15 LSU1 SRQ lhs rejects 1 Group 15 pm_prefetch4
PM_DC_PREF_DST_GRP15 DST (Data Stream Touch) stream start 2 Group 15 pm_prefetch4
PM_L2_PREF_GRP15 L2 cache prefetches 3 Group 15 pm_prefetch4
PM_LSU_REJECT_ERAT_MISS_GRP16 LSU reject due to ERAT miss 0 Group 16 pm_lsu_reject1
PM_LSU_REJECT_LMQ_FULL_GRP16 LSU reject due to LMQ full or missed data coming 1 Group 16 pm_lsu_reject1
PM_FLUSH_IMBAL_GRP16 Flush caused by thread GCT imbalance 2 Group 16 pm_lsu_reject1
PM_MRK_LSU_FLUSH_SRQ_GRP16 Marked SRQ lhs flushes 3 Group 16 pm_lsu_reject1
PM_LSU0_REJECT_RELOAD_CDF_GRP17 LSU0 reject due to reload CDF or tag update collision 0 Group 17 pm_lsu_reject2
PM_LSU1_REJECT_RELOAD_CDF_GRP17 LSU1 reject due to reload CDF or tag update collision 1 Group 17 pm_lsu_reject2
PM_IOPS_CMPL_GRP17 Internal operations completed 2 Group 17 pm_lsu_reject2
PM_L1_WRITE_CYC_GRP17 Cycles writing to instruction L1 3 Group 17 pm_lsu_reject2
PM_LSU0_REJECT_ERAT_MISS_GRP18 LSU0 reject due to ERAT miss 0 Group 18 pm_lsu_reject3
PM_LSU1_REJECT_ERAT_MISS_GRP18 LSU1 reject due to ERAT miss 1 Group 18 pm_lsu_reject3
PM_LWSYNC_HELD_GRP18 LWSYNC held at dispatch 2 Group 18 pm_lsu_reject3
PM_TLBIE_HELD_GRP18 TLBIE held at dispatch 3 Group 18 pm_lsu_reject3
PM_LSU0_REJECT_LMQ_FULL_GRP19 LSU0 reject due to LMQ full or missed data coming 0 Group 19 pm_lsu_reject4
PM_LSU1_REJECT_LMQ_FULL_GRP19 LSU1 reject due to LMQ full or missed data coming 1 Group 19 pm_lsu_reject4
PM_IOPS_CMPL_GRP19 Internal operations completed 2 Group 19 pm_lsu_reject4
PM_BR_ISSUED_GRP19 Branches issued 3 Group 19 pm_lsu_reject4
PM_LSU_REJECT_SRQ_GRP20 LSU SRQ lhs rejects 0 Group 20 pm_lsu_reject5
PM_LSU_REJECT_RELOAD_CDF_GRP20 LSU reject due to reload CDF or tag update collision 1 Group 20 pm_lsu_reject5
PM_LSU_FLUSH_GRP20 Flush initiated by LSU 2 Group 20 pm_lsu_reject5
PM_FLUSH_GRP20 Flushes 3 Group 20 pm_lsu_reject5
PM_IOPS_CMPL_GRP21 Internal operations completed 0 Group 21 pm_flush1
PM_LSU_FLUSH_UST_GRP21 SRQ unaligned store flushes 1 Group 21 pm_flush1
PM_FLUSH_IMBAL_GRP21 Flush caused by thread GCT imbalance 2 Group 21 pm_flush1
PM_DC_INV_L2_GRP21 L1 D cache entries invalidated from L2 3 Group 21 pm_flush1
PM_ITLB_MISS_GRP22 Instruction TLB misses 0 Group 22 pm_flush2
PM_IOPS_CMPL_GRP22 Internal operations completed 1 Group 22 pm_flush2
PM_FLUSH_SB_GRP22 Flush caused by scoreboard operation 2 Group 22 pm_flush2
PM_FLUSH_SYNC_GRP22 Flush caused by sync 3 Group 22 pm_flush2
PM_LSU_FLUSH_SRQ_GRP23 SRQ flushes 0 Group 23 pm_lsu_flush_srq_lrq
PM_LSU_FLUSH_LRQ_GRP23 LRQ flushes 1 Group 23 pm_lsu_flush_srq_lrq
PM_IOPS_CMPL_GRP23 Internal operations completed 2 Group 23 pm_lsu_flush_srq_lrq
PM_LSU_FLUSH_GRP23 Flush initiated by LSU 3 Group 23 pm_lsu_flush_srq_lrq
PM_LSU0_FLUSH_LRQ_GRP24 LSU0 LRQ flushes 0 Group 24 pm_lsu_flush_lrq
PM_LSU1_FLUSH_LRQ_GRP24 LSU1 LRQ flushes 1 Group 24 pm_lsu_flush_lrq
PM_LSU_FLUSH_GRP24 Flush initiated by LSU 2 Group 24 pm_lsu_flush_lrq
PM_IOPS_CMPL_GRP24 Internal operations completed 3 Group 24 pm_lsu_flush_lrq
PM_LSU0_FLUSH_SRQ_GRP25 LSU0 SRQ lhs flushes 0 Group 25 pm_lsu_flush_srq
PM_LSU1_FLUSH_SRQ_GRP25 LSU1 SRQ lhs flushes 1 Group 25 pm_lsu_flush_srq
PM_IOPS_CMPL_GRP25 Internal operations completed 2 Group 25 pm_lsu_flush_srq
PM_LSU_FLUSH_GRP25 Flush initiated by LSU 3 Group 25 pm_lsu_flush_srq
PM_LSU_FLUSH_ULD_GRP26 LRQ unaligned load flushes 0 Group 26 pm_lsu_flush_unaligned
PM_LSU_FLUSH_UST_GRP26 SRQ unaligned store flushes 1 Group 26 pm_lsu_flush_unaligned
PM_BR_ISSUED_GRP26 Branches issued 2 Group 26 pm_lsu_flush_unaligned
PM_IOPS_CMPL_GRP26 Internal operations completed 3 Group 26 pm_lsu_flush_unaligned
PM_LSU0_FLUSH_ULD_GRP27 LSU0 unaligned load flushes 0 Group 27 pm_lsu_flush_uld
PM_LSU1_FLUSH_ULD_GRP27 LSU1 unaligned load flushes 1 Group 27 pm_lsu_flush_uld
PM_LSU_FLUSH_GRP27 Flush initiated by LSU 2 Group 27 pm_lsu_flush_uld
PM_IOPS_CMPL_GRP27 Internal operations completed 3 Group 27 pm_lsu_flush_uld
PM_LSU0_FLUSH_UST_GRP28 LSU0 unaligned store flushes 0 Group 28 pm_lsu_flush_ust
PM_LSU1_FLUSH_UST_GRP28 LSU1 unaligned store flushes 1 Group 28 pm_lsu_flush_ust
PM_IOPS_CMPL_GRP28 Internal operations completed 2 Group 28 pm_lsu_flush_ust
PM_LSU_FLUSH_GRP28 Flush initiated by LSU 3 Group 28 pm_lsu_flush_ust
PM_LSU_FLUSH_LRQ_FULL_GRP29 Flush caused by LRQ full 0 Group 29 pm_lsu_flush_full
PM_IOPS_CMPL_GRP29 Internal operations completed 1 Group 29 pm_lsu_flush_full
PM_MRK_LSU_FLUSH_LRQ_GRP29 Marked LRQ flushes 2 Group 29 pm_lsu_flush_full
PM_LSU_FLUSH_SRQ_FULL_GRP29 Flush caused by SRQ full 3 Group 29 pm_lsu_flush_full
PM_GRP_MRK_GRP30 Group marked in IDU 0 Group 30 pm_lsu_stall1
PM_CMPLU_STALL_LSU_GRP30 Completion stall caused by LSU instruction 1 Group 30 pm_lsu_stall1
PM_IOPS_CMPL_GRP30 Internal operations completed 2 Group 30 pm_lsu_stall1
PM_CMPLU_STALL_REJECT_GRP30 Completion stall caused by reject 3 Group 30 pm_lsu_stall1
PM_IOPS_CMPL_GRP31 Internal operations completed 0 Group 31 pm_lsu_stall2
PM_CMPLU_STALL_DCACHE_MISS_GRP31 Completion stall caused by D cache miss 1 Group 31 pm_lsu_stall2
PM_CYC_GRP31 Processor cycles 2 Group 31 pm_lsu_stall2
PM_CMPLU_STALL_ERAT_MISS_GRP31 Completion stall caused by ERAT miss 3 Group 31 pm_lsu_stall2
PM_GRP_IC_MISS_BR_REDIR_NONSPEC_GRP32 Group experienced non-speculative I cache miss or branch redirect 0 Group 32 pm_fxu_stall
PM_CMPLU_STALL_FXU_GRP32 Completion stall caused by FXU instruction 1 Group 32 pm_fxu_stall
PM_IOPS_CMPL_GRP32 Internal operations completed 2 Group 32 pm_fxu_stall
PM_CMPLU_STALL_DIV_GRP32 Completion stall caused by DIV instruction 3 Group 32 pm_fxu_stall
PM_FPU_FULL_CYC_GRP33 Cycles FPU issue queue full 0 Group 33 pm_fpu_stall
PM_CMPLU_STALL_FDIV_GRP33 Completion stall caused by FDIV or FQRT instruction 1 Group 33 pm_fpu_stall
PM_IOPS_CMPL_GRP33 Internal operations completed 2 Group 33 pm_fpu_stall
PM_CMPLU_STALL_FPU_GRP33 Completion stall caused by FPU instruction 3 Group 33 pm_fpu_stall
PM_LARX_LSU0_GRP34 Larx executed on LSU0 0 Group 34 pm_queue_full
PM_BRQ_FULL_CYC_GRP34 Cycles branch queue full 1 Group 34 pm_queue_full
PM_LSU_LRQ_FULL_CYC_GRP34 Cycles LRQ full 2 Group 34 pm_queue_full
PM_LSU_LMQ_FULL_CYC_GRP34 Cycles LMQ full 3 Group 34 pm_queue_full
PM_FPU0_FULL_CYC_GRP35 Cycles FPU0 issue queue full 0 Group 35 pm_issueq_full
PM_FPU1_FULL_CYC_GRP35 Cycles FPU1 issue queue full 1 Group 35 pm_issueq_full
PM_FXLS0_FULL_CYC_GRP35 Cycles FXU0/LS0 queue full 2 Group 35 pm_issueq_full
PM_FXLS1_FULL_CYC_GRP35 Cycles FXU1/LS1 queue full 3 Group 35 pm_issueq_full
PM_CR_MAP_FULL_CYC_GRP36 Cycles CR logical operation mapper full 0 Group 36 pm_mapper_full1
PM_LR_CTR_MAP_FULL_CYC_GRP36 Cycles LR/CTR mapper full 1 Group 36 pm_mapper_full1
PM_GPR_MAP_FULL_CYC_GRP36 Cycles GPR mapper full 2 Group 36 pm_mapper_full1
PM_CRQ_FULL_CYC_GRP36 Cycles CR issue queue full 3 Group 36 pm_mapper_full1
PM_FPR_MAP_FULL_CYC_GRP37 Cycles FPR mapper full 0 Group 37 pm_mapper_full2
PM_XER_MAP_FULL_CYC_GRP37 Cycles XER mapper full 1 Group 37 pm_mapper_full2
PM_MRK_DATA_FROM_L2MISS_GRP37 Marked data loaded missed L2 2 Group 37 pm_mapper_full2
PM_IOPS_CMPL_GRP37 Internal operations completed 3 Group 37 pm_mapper_full2
PM_STCX_FAIL_GRP38 STCX failed 0 Group 38 pm_misc_load
PM_STCX_PASS_GRP38 Stcx passes 1 Group 38 pm_misc_load
PM_LSU0_NCLD_GRP38 LSU0 non-cacheable loads 2 Group 38 pm_misc_load
PM_LSU1_NCLD_GRP38 LSU1 non-cacheable loads 3 Group 38 pm_misc_load
PM_LSU0_BUSY_REJECT_GRP39 LSU0 busy due to reject 0 Group 39 pm_ic_demand
PM_LSU1_BUSY_REJECT_GRP39 LSU1 busy due to reject 1 Group 39 pm_ic_demand
PM_IC_DEMAND_L2_BHT_REDIRECT_GRP39 L2 I cache demand request due to BHT redirect 2 Group 39 pm_ic_demand
PM_IC_DEMAND_L2_BR_REDIRECT_GRP39 L2 I cache demand request due to branch redirect 3 Group 39 pm_ic_demand
PM_IERAT_XLATE_WR_GRP40 Translation written to ierat 0 Group 40 pm_ic_pref
PM_IC_PREF_REQ_GRP40 Instruction prefetch requests 1 Group 40 pm_ic_pref
PM_IC_PREF_INSTALL_GRP40 Instruction prefetched installed in prefetch buffer 2 Group 40 pm_ic_pref
PM_0INST_FETCH_GRP40 No instructions fetched 3 Group 40 pm_ic_pref
PM_GRP_IC_MISS_NONSPEC_GRP41 Group experienced non-speculative I cache miss 0 Group 41 pm_ic_miss
PM_GRP_IC_MISS_GRP41 Group experienced I cache miss 1 Group 41 pm_ic_miss
PM_L1_DCACHE_RELOAD_VALID_GRP41 L1 reload data source valid 2 Group 41 pm_ic_miss
PM_IOPS_CMPL_GRP41 Internal operations completed 3 Group 41 pm_ic_miss
PM_TLB_MISS_GRP42 TLB misses 0 Group 42 pm_branch_miss
PM_SLB_MISS_GRP42 SLB misses 1 Group 42 pm_branch_miss
PM_BR_MPRED_CR_GRP42 Branch mispredictions due to CR bit setting 2 Group 42 pm_branch_miss
PM_BR_MPRED_TA_GRP42 Branch mispredictions due to target address 3 Group 42 pm_branch_miss
PM_BR_UNCOND_GRP43 Unconditional branch 0 Group 43 pm_branch1
PM_BR_PRED_TA_GRP43 A conditional branch was predicted, target prediction 1 Group 43 pm_branch1
PM_BR_PRED_CR_GRP43 A conditional branch was predicted, CR prediction 2 Group 43 pm_branch1
PM_BR_PRED_CR_TA_GRP43 A conditional branch was predicted, CR and target prediction 3 Group 43 pm_branch1
PM_GRP_BR_REDIR_NONSPEC_GRP44 Group experienced non-speculative branch redirect 0 Group 44 pm_branch2
PM_GRP_BR_REDIR_GRP44 Group experienced branch redirect 1 Group 44 pm_branch2
PM_FLUSH_BR_MPRED_GRP44 Flush caused by branch mispredict 2 Group 44 pm_branch2
PM_IOPS_CMPL_GRP44 Internal operations completed 3 Group 44 pm_branch2
PM_DATA_TABLEWALK_CYC_GRP45 Cycles doing data tablewalks 0 Group 45 pm_L1_tlbmiss
PM_DTLB_MISS_GRP45 Data TLB misses 1 Group 45 pm_L1_tlbmiss
PM_LD_MISS_L1_GRP45 L1 D cache load misses 2 Group 45 pm_L1_tlbmiss
PM_LD_REF_L1_GRP45 L1 D cache load references 3 Group 45 pm_L1_tlbmiss
PM_DATA_FROM_L2_GRP46 Data loaded from L2 0 Group 46 pm_L1_DERAT_miss
PM_LSU_DERAT_MISS_GRP46 DERAT misses 1 Group 46 pm_L1_DERAT_miss
PM_ST_REF_L1_GRP46 L1 D cache store references 2 Group 46 pm_L1_DERAT_miss
PM_ST_MISS_L1_GRP46 L1 D cache store misses 3 Group 46 pm_L1_DERAT_miss
PM_DSLB_MISS_GRP47 Data SLB misses 0 Group 47 pm_L1_slbmiss
PM_ISLB_MISS_GRP47 Instruction SLB misses 1 Group 47 pm_L1_slbmiss
PM_LD_MISS_L1_LSU0_GRP47 LSU0 L1 D cache load misses 2 Group 47 pm_L1_slbmiss
PM_LD_MISS_L1_LSU1_GRP47 LSU1 L1 D cache load misses 3 Group 47 pm_L1_slbmiss
PM_DTLB_REF_4K_GRP48 Data TLB reference for 4K page 0 Group 48 pm_dtlbref
PM_DTLB_REF_64K_GRP48 Data TLB reference for 64K page 1 Group 48 pm_dtlbref
PM_DTLB_REF_16M_GRP48 Data TLB reference for 16M page 2 Group 48 pm_dtlbref
PM_DTLB_REF_16G_GRP48 Data TLB reference for 16G page 3 Group 48 pm_dtlbref
PM_DTLB_MISS_4K_GRP49 Data TLB miss for 4K page 0 Group 49 pm_dtlbmiss
PM_DTLB_MISS_64K_GRP49 Data TLB miss for 64K page 1 Group 49 pm_dtlbmiss
PM_DTLB_MISS_16M_GRP49 Data TLB miss for 16M page 2 Group 49 pm_dtlbmiss
PM_DTLB_MISS_16G_GRP49 Data TLB miss for 16G page 3 Group 49 pm_dtlbmiss
PM_DTLB_REF_GRP50 Data TLB references 0 Group 50 pm_dtlb
PM_DTLB_MISS_GRP50 Data TLB misses 1 Group 50 pm_dtlb
PM_CYC_GRP50 Processor cycles 2 Group 50 pm_dtlb
PM_CYC_GRP50 Processor cycles 3 Group 50 pm_dtlb
PM_LD_REF_L1_GRP51 L1 D cache load references 0 Group 51 pm_L1_refmiss
PM_ST_REF_L1_GRP51 L1 D cache store references 1 Group 51 pm_L1_refmiss
PM_LD_MISS_L1_GRP51 L1 D cache load misses 2 Group 51 pm_L1_refmiss
PM_ST_MISS_L1_GRP51 L1 D cache store misses 3 Group 51 pm_L1_refmiss
PM_DATA_FROM_L3_GRP52 Data loaded from L3 0 Group 52 pm_dsource1
PM_DATA_FROM_LMEM_GRP52 Data loaded from local memory 1 Group 52 pm_dsource1
PM_FLUSH_GRP52 Flushes 2 Group 52 pm_dsource1
PM_IOPS_CMPL_GRP52 Internal operations completed 3 Group 52 pm_dsource1
PM_DATA_FROM_L3_GRP53 Data loaded from L3 0 Group 53 pm_dsource2
PM_DATA_FROM_LMEM_GRP53 Data loaded from local memory 1 Group 53 pm_dsource2
PM_DATA_FROM_L2MISS_GRP53 Data loaded missed L2 2 Group 53 pm_dsource2
PM_DATA_FROM_RMEM_GRP53 Data loaded from remote memory 3 Group 53 pm_dsource2
PM_DATA_FROM_L25_SHR_GRP54 Data loaded from L2.5 shared 0 Group 54 pm_dsource_L2
PM_DATA_FROM_L25_MOD_GRP54 Data loaded from L2.5 modified 1 Group 54 pm_dsource_L2
PM_DATA_FROM_L275_SHR_GRP54 Data loaded from L2.75 shared 2 Group 54 pm_dsource_L2
PM_DATA_FROM_L275_MOD_GRP54 Data loaded from L2.75 modified 3 Group 54 pm_dsource_L2
PM_DATA_FROM_L35_SHR_GRP55 Data loaded from L3.5 shared 0 Group 55 pm_dsource_L3
PM_DATA_FROM_L35_MOD_GRP55 Data loaded from L3.5 modified 1 Group 55 pm_dsource_L3
PM_DATA_FROM_L375_SHR_GRP55 Data loaded from L3.75 shared 2 Group 55 pm_dsource_L3
PM_DATA_FROM_L375_MOD_GRP55 Data loaded from L3.75 modified 3 Group 55 pm_dsource_L3
PM_INST_FROM_L3_GRP56 Instruction fetched from L3 0 Group 56 pm_isource1
PM_INST_FROM_L1_GRP56 Instruction fetched from L1 1 Group 56 pm_isource1
PM_INST_FROM_PREF_GRP56 Instruction fetched from prefetch 2 Group 56 pm_isource1
PM_INST_FROM_RMEM_GRP56 Instruction fetched from remote memory 3 Group 56 pm_isource1
PM_INST_FROM_L2_GRP57 Instruction fetched from L2 0 Group 57 pm_isource2
PM_INST_FROM_LMEM_GRP57 Instruction fetched from local memory 1 Group 57 pm_isource2
PM_IOPS_CMPL_GRP57 Internal operations completed 2 Group 57 pm_isource2
PM_0INST_FETCH_GRP57 No instructions fetched 3 Group 57 pm_isource2
PM_INST_FROM_L25_SHR_GRP58 Instruction fetched from L2.5 shared 0 Group 58 pm_isource_L2
PM_INST_FROM_L25_MOD_GRP58 Instruction fetched from L2.5 modified 1 Group 58 pm_isource_L2
PM_INST_FROM_L275_SHR_GRP58 Instruction fetched from L2.75 shared 2 Group 58 pm_isource_L2
PM_INST_FROM_L275_MOD_GRP58 Instruction fetched from L2.75 modified 3 Group 58 pm_isource_L2
PM_INST_FROM_L35_SHR_GRP59 Instruction fetched from L3.5 shared 0 Group 59 pm_isource_L3
PM_INST_FROM_L35_MOD_GRP59 Instruction fetched from L3.5 modified 1 Group 59 pm_isource_L3
PM_INST_FROM_L375_SHR_GRP59 Instruction fetched from L3.75 shared 2 Group 59 pm_isource_L3
PM_INST_FROM_L375_MOD_GRP59 Instruction fetched from L3.75 modified 3 Group 59 pm_isource_L3
PM_PTEG_FROM_L25_SHR_GRP60 PTEG loaded from L2.5 shared 0 Group 60 pm_pteg_source1
PM_PTEG_FROM_L25_MOD_GRP60 PTEG loaded from L2.5 modified 1 Group 60 pm_pteg_source1
PM_PTEG_FROM_L275_SHR_GRP60 PTEG loaded from L2.75 shared 2 Group 60 pm_pteg_source1
PM_PTEG_FROM_L275_MOD_GRP60 PTEG loaded from L2.75 modified 3 Group 60 pm_pteg_source1
PM_PTEG_FROM_L35_SHR_GRP61 PTEG loaded from L3.5 shared 0 Group 61 pm_pteg_source2
PM_PTEG_FROM_L35_MOD_GRP61 PTEG loaded from L3.5 modified 1 Group 61 pm_pteg_source2
PM_PTEG_FROM_L375_SHR_GRP61 PTEG loaded from L3.75 shared 2 Group 61 pm_pteg_source2
PM_PTEG_FROM_L375_MOD_GRP61 PTEG loaded from L3.75 modified 3 Group 61 pm_pteg_source2
PM_PTEG_FROM_L2_GRP62 PTEG loaded from L2 0 Group 62 pm_pteg_source3
PM_PTEG_FROM_LMEM_GRP62 PTEG loaded from local memory 1 Group 62 pm_pteg_source3
PM_PTEG_FROM_L2MISS_GRP62 PTEG loaded from L2 miss 2 Group 62 pm_pteg_source3
PM_PTEG_FROM_RMEM_GRP62 PTEG loaded from remote memory 3 Group 62 pm_pteg_source3
PM_PTEG_FROM_L3_GRP63 PTEG loaded from L3 0 Group 63 pm_pteg_source4
PM_GRP_DISP_GRP63 Group dispatches 1 Group 63 pm_pteg_source4
PM_GRP_DISP_SUCCESS_GRP63 Group dispatch success 2 Group 63 pm_pteg_source4
PM_DC_INV_L2_GRP63 L1 D cache entries invalidated from L2 3 Group 63 pm_pteg_source4
PM_L2SA_RCLD_DISP_GRP64 L2 slice A RC load dispatch attempt 0 Group 64 pm_L2SA_ld
PM_L2SA_RCLD_DISP_FAIL_RC_FULL_GRP64 L2 slice A RC load dispatch attempt failed due to all RC full 1 Group 64 pm_L2SA_ld
PM_L2SA_RCLD_DISP_FAIL_ADDR_GRP64 L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ 2 Group 64 pm_L2SA_ld
PM_L2SA_RCLD_DISP_FAIL_OTHER_GRP64 L2 slice A RC load dispatch attempt failed due to other reasons 3 Group 64 pm_L2SA_ld
PM_L2SA_RCST_DISP_GRP65 L2 slice A RC store dispatch attempt 0 Group 65 pm_L2SA_st
PM_L2SA_RCST_DISP_FAIL_RC_FULL_GRP65 L2 slice A RC store dispatch attempt failed due to all RC full 1 Group 65 pm_L2SA_st
PM_L2SA_RCST_DISP_FAIL_ADDR_GRP65 L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ 2 Group 65 pm_L2SA_st
PM_L2SA_RCST_DISP_FAIL_OTHER_GRP65 L2 slice A RC store dispatch attempt failed due to other reasons 3 Group 65 pm_L2SA_st
PM_L2SA_RC_DISP_FAIL_CO_BUSY_GRP66 L2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy 0 Group 66 pm_L2SA_st2
PM_L2SA_ST_REQ_GRP66 L2 slice A store requests 1 Group 66 pm_L2SA_st2
PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL_GRP66 L2 slice A RC dispatch attempt failed due to all CO busy 2 Group 66 pm_L2SA_st2
PM_L2SA_ST_HIT_GRP66 L2 slice A store hits 3 Group 66 pm_L2SA_st2
PM_L2SB_RCLD_DISP_GRP67 L2 slice B RC load dispatch attempt 0 Group 67 pm_L2SB_ld
PM_L2SB_RCLD_DISP_FAIL_RC_FULL_GRP67 L2 slice B RC load dispatch attempt failed due to all RC full 1 Group 67 pm_L2SB_ld
PM_L2SB_RCLD_DISP_FAIL_ADDR_GRP67 L2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ 2 Group 67 pm_L2SB_ld
PM_L2SB_RCLD_DISP_FAIL_OTHER_GRP67 L2 slice B RC load dispatch attempt failed due to other reasons 3 Group 67 pm_L2SB_ld
PM_L2SB_RCST_DISP_GRP68 L2 slice B RC store dispatch attempt 0 Group 68 pm_L2SB_st
PM_L2SB_RCST_DISP_FAIL_RC_FULL_GRP68 L2 slice B RC store dispatch attempt failed due to all RC full 1 Group 68 pm_L2SB_st
PM_L2SB_RCST_DISP_FAIL_ADDR_GRP68 L2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ 2 Group 68 pm_L2SB_st
PM_L2SB_RCST_DISP_FAIL_OTHER_GRP68 L2 slice B RC store dispatch attempt failed due to other reasons 3 Group 68 pm_L2SB_st
PM_L2SB_RC_DISP_FAIL_CO_BUSY_GRP69 L2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy 0 Group 69 pm_L2SB_st2
PM_L2SB_ST_REQ_GRP69 L2 slice B store requests 1 Group 69 pm_L2SB_st2
PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL_GRP69 L2 slice B RC dispatch attempt failed due to all CO busy 2 Group 69 pm_L2SB_st2
PM_L2SB_ST_HIT_GRP69 L2 slice B store hits 3 Group 69 pm_L2SB_st2
PM_L2SC_RCLD_DISP_GRP70 L2 slice C RC load dispatch attempt 0 Group 70 pm_L2SC_ld
PM_L2SC_RCLD_DISP_FAIL_RC_FULL_GRP70 L2 slice C RC load dispatch attempt failed due to all RC full 1 Group 70 pm_L2SC_ld
PM_L2SC_RCLD_DISP_FAIL_ADDR_GRP70 L2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ 2 Group 70 pm_L2SC_ld
PM_L2SC_RCLD_DISP_FAIL_OTHER_GRP70 L2 slice C RC load dispatch attempt failed due to other reasons 3 Group 70 pm_L2SC_ld
PM_L2SC_RCST_DISP_GRP71 L2 slice C RC store dispatch attempt 0 Group 71 pm_L2SC_st
PM_L2SC_RCST_DISP_FAIL_RC_FULL_GRP71 L2 slice C RC store dispatch attempt failed due to all RC full 1 Group 71 pm_L2SC_st
PM_L2SC_RCST_DISP_FAIL_ADDR_GRP71 L2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ 2 Group 71 pm_L2SC_st
PM_L2SC_RCST_DISP_FAIL_OTHER_GRP71 L2 slice C RC store dispatch attempt failed due to other reasons 3 Group 71 pm_L2SC_st
PM_L2SC_RC_DISP_FAIL_CO_BUSY_GRP72 L2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy 0 Group 72 pm_L2SC_st2
PM_L2SC_ST_REQ_GRP72 L2 slice C store requests 1 Group 72 pm_L2SC_st2
PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL_GRP72 L2 slice C RC dispatch attempt failed due to all CO busy 2 Group 72 pm_L2SC_st2
PM_L2SC_ST_HIT_GRP72 L2 slice C store hits 3 Group 72 pm_L2SC_st2
PM_L3SA_MOD_TAG_GRP73 L3 slice A transition from modified to TAG 0 Group 73 pm_L3SA_trans
PM_IOPS_CMPL_GRP73 Internal operations completed 1 Group 73 pm_L3SA_trans
PM_L3SA_MOD_INV_GRP73 L3 slice A transition from modified to invalid 2 Group 73 pm_L3SA_trans
PM_L3SA_SHR_INV_GRP73 L3 slice A transition from shared to invalid 3 Group 73 pm_L3SA_trans
PM_IOPS_CMPL_GRP74 Internal operations completed 0 Group 74 pm_L3SB_trans
PM_L3SB_MOD_TAG_GRP74 L3 slice B transition from modified to TAG 1 Group 74 pm_L3SB_trans
PM_L3SB_MOD_INV_GRP74 L3 slice B transition from modified to invalid 2 Group 74 pm_L3SB_trans
PM_L3SB_SHR_INV_GRP74 L3 slice B transition from shared to invalid 3 Group 74 pm_L3SB_trans
PM_IOPS_CMPL_GRP75 Internal operations completed 0 Group 75 pm_L3SC_trans
PM_L3SC_MOD_TAG_GRP75 L3 slice C transition from modified to TAG 1 Group 75 pm_L3SC_trans
PM_L3SC_MOD_INV_GRP75 L3 slice C transition from modified to invalid 2 Group 75 pm_L3SC_trans
PM_L3SC_SHR_INV_GRP75 L3 slice C transition from shared to invalid 3 Group 75 pm_L3SC_trans
PM_L2SA_MOD_TAG_GRP76 L2 slice A transition from modified to tagged 0 Group 76 pm_L2SA_trans
PM_L2SA_SHR_MOD_GRP76 L2 slice A transition from shared to modified 1 Group 76 pm_L2SA_trans
PM_L2SA_MOD_INV_GRP76 L2 slice A transition from modified to invalid 2 Group 76 pm_L2SA_trans
PM_L2SA_SHR_INV_GRP76 L2 slice A transition from shared to invalid 3 Group 76 pm_L2SA_trans
PM_L2SB_MOD_TAG_GRP77 L2 slice B transition from modified to tagged 0 Group 77 pm_L2SB_trans
PM_L2SB_SHR_MOD_GRP77 L2 slice B transition from shared to modified 1 Group 77 pm_L2SB_trans
PM_L2SB_MOD_INV_GRP77 L2 slice B transition from modified to invalid 2 Group 77 pm_L2SB_trans
PM_L2SB_SHR_INV_GRP77 L2 slice B transition from shared to invalid 3 Group 77 pm_L2SB_trans
PM_L2SC_MOD_TAG_GRP78 L2 slice C transition from modified to tagged 0 Group 78 pm_L2SC_trans
PM_L2SC_SHR_MOD_GRP78 L2 slice C transition from shared to modified 1 Group 78 pm_L2SC_trans
PM_L2SC_MOD_INV_GRP78 L2 slice C transition from modified to invalid 2 Group 78 pm_L2SC_trans
PM_L2SC_SHR_INV_GRP78 L2 slice C transition from shared to invalid 3 Group 78 pm_L2SC_trans
PM_L3SA_ALL_BUSY_GRP79 L3 slice A active for every cycle all CI/CO machines busy 0 Group 79 pm_L3SAB_retry
PM_L3SB_ALL_BUSY_GRP79 L3 slice B active for every cycle all CI/CO machines busy 1 Group 79 pm_L3SAB_retry
PM_L3SA_SNOOP_RETRY_GRP79 L3 slice A snoop retries 2 Group 79 pm_L3SAB_retry
PM_L3SB_SNOOP_RETRY_GRP79 L3 slice B snoop retries 3 Group 79 pm_L3SAB_retry
PM_L3SA_REF_GRP80 L3 slice A references 0 Group 80 pm_L3SAB_hit
PM_L3SB_REF_GRP80 L3 slice B references 1 Group 80 pm_L3SAB_hit
PM_L3SA_HIT_GRP80 L3 slice A hits 2 Group 80 pm_L3SAB_hit
PM_L3SB_HIT_GRP80 L3 slice B hits 3 Group 80 pm_L3SAB_hit
PM_L3SC_ALL_BUSY_GRP81 L3 slice C active for every cycle all CI/CO machines busy 0 Group 81 pm_L3SC_retry_hit
PM_L3SC_REF_GRP81 L3 slice C references 1 Group 81 pm_L3SC_retry_hit
PM_L3SC_SNOOP_RETRY_GRP81 L3 slice C snoop retries 2 Group 81 pm_L3SC_retry_hit
PM_L3SC_HIT_GRP81 L3 slice C hits 3 Group 81 pm_L3SC_retry_hit
PM_FPU_FDIV_GRP82 FPU executed FDIV instruction 0 Group 82 pm_fpu1
PM_FPU_FMA_GRP82 FPU executed multiply-add instruction 1 Group 82 pm_fpu1
PM_FPU_FMOV_FEST_GRP82 FPU executed FMOV or FEST instructions 2 Group 82 pm_fpu1
PM_FPU_FEST_GRP82 FPU executed FEST instruction 3 Group 82 pm_fpu1
PM_FPU_1FLOP_GRP83 FPU executed one flop instruction 0 Group 83 pm_fpu2
PM_FPU_FSQRT_GRP83 FPU executed FSQRT instruction 1 Group 83 pm_fpu2
PM_FPU_FRSP_FCONV_GRP83 FPU executed FRSP or FCONV instructions 2 Group 83 pm_fpu2
PM_FPU_FIN_GRP83 FPU produced a result 3 Group 83 pm_fpu2
PM_FPU_DENORM_GRP84 FPU received denormalized data 0 Group 84 pm_fpu3
PM_FPU_STALL3_GRP84 FPU stalled in pipe3 1 Group 84 pm_fpu3
PM_FPU0_FIN_GRP84 FPU0 produced a result 2 Group 84 pm_fpu3
PM_FPU1_FIN_GRP84 FPU1 produced a result 3 Group 84 pm_fpu3
PM_FPU_SINGLE_GRP85 FPU executed single precision instruction 0 Group 85 pm_fpu4
PM_FPU_STF_GRP85 FPU executed store instruction 1 Group 85 pm_fpu4
PM_IOPS_CMPL_GRP85 Internal operations completed 2 Group 85 pm_fpu4
PM_LSU_LDF_GRP85 LSU executed Floating Point load instruction 3 Group 85 pm_fpu4
PM_FPU0_FSQRT_GRP86 FPU0 executed FSQRT instruction 0 Group 86 pm_fpu5
PM_FPU1_FSQRT_GRP86 FPU1 executed FSQRT instruction 1 Group 86 pm_fpu5
PM_FPU0_FEST_GRP86 FPU0 executed FEST instruction 2 Group 86 pm_fpu5
PM_FPU1_FEST_GRP86 FPU1 executed FEST instruction 3 Group 86 pm_fpu5
PM_FPU0_DENORM_GRP87 FPU0 received denormalized data 0 Group 87 pm_fpu6
PM_FPU1_DENORM_GRP87 FPU1 received denormalized data 1 Group 87 pm_fpu6
PM_FPU0_FMOV_FEST_GRP87 FPU0 executed FMOV or FEST instructions 2 Group 87 pm_fpu6
PM_FPU1_FMOV_FEST_GRP87 FPU1 executed FMOV or FEST instructions 3 Group 87 pm_fpu6
PM_FPU0_FDIV_GRP88 FPU0 executed FDIV instruction 0 Group 88 pm_fpu7
PM_FPU1_FDIV_GRP88 FPU1 executed FDIV instruction 1 Group 88 pm_fpu7
PM_FPU0_FRSP_FCONV_GRP88 FPU0 executed FRSP or FCONV instructions 2 Group 88 pm_fpu7
PM_FPU1_FRSP_FCONV_GRP88 FPU1 executed FRSP or FCONV instructions 3 Group 88 pm_fpu7
PM_FPU0_STALL3_GRP89 FPU0 stalled in pipe3 0 Group 89 pm_fpu8
PM_FPU1_STALL3_GRP89 FPU1 stalled in pipe3 1 Group 89 pm_fpu8
PM_IOPS_CMPL_GRP89 Internal operations completed 2 Group 89 pm_fpu8
PM_FPU0_FPSCR_GRP89 FPU0 executed FPSCR instruction 3 Group 89 pm_fpu8
PM_FPU0_SINGLE_GRP90 FPU0 executed single precision instruction 0 Group 90 pm_fpu9
PM_FPU1_SINGLE_GRP90 FPU1 executed single precision instruction 1 Group 90 pm_fpu9
PM_LSU0_LDF_GRP90 LSU0 executed Floating Point load instruction 2 Group 90 pm_fpu9
PM_LSU1_LDF_GRP90 LSU1 executed Floating Point load instruction 3 Group 90 pm_fpu9
PM_FPU0_FMA_GRP91 FPU0 executed multiply-add instruction 0 Group 91 pm_fpu10
PM_FPU1_FMA_GRP91 FPU1 executed multiply-add instruction 1 Group 91 pm_fpu10
PM_IOPS_CMPL_GRP91 Internal operations completed 2 Group 91 pm_fpu10
PM_FPU1_FRSP_FCONV_GRP91 FPU1 executed FRSP or FCONV instructions 3 Group 91 pm_fpu10
PM_FPU0_1FLOP_GRP92 FPU0 executed add, mult, sub, cmp or sel instruction 0 Group 92 pm_fpu11
PM_FPU1_1FLOP_GRP92 FPU1 executed add, mult, sub, cmp or sel instruction 1 Group 92 pm_fpu11
PM_FPU0_FIN_GRP92 FPU0 produced a result 2 Group 92 pm_fpu11
PM_IOPS_CMPL_GRP92 Internal operations completed 3 Group 92 pm_fpu11
PM_FPU0_STF_GRP93 FPU0 executed store instruction 0 Group 93 pm_fpu12
PM_FPU1_STF_GRP93 FPU1 executed store instruction 1 Group 93 pm_fpu12
PM_LSU0_LDF_GRP93 LSU0 executed Floating Point load instruction 2 Group 93 pm_fpu12
PM_IOPS_CMPL_GRP93 Internal operations completed 3 Group 93 pm_fpu12
PM_FXU_IDLE_GRP94 FXU idle 0 Group 94 pm_fxu1
PM_FXU_BUSY_GRP94 FXU busy 1 Group 94 pm_fxu1
PM_FXU0_BUSY_FXU1_IDLE_GRP94 FXU0 busy FXU1 idle 2 Group 94 pm_fxu1
PM_FXU1_BUSY_FXU0_IDLE_GRP94 FXU1 busy FXU0 idle 3 Group 94 pm_fxu1
PM_MRK_GRP_DISP_GRP95 Marked group dispatched 0 Group 95 pm_fxu2
PM_MRK_GRP_BR_REDIR_GRP95 Group experienced marked branch redirect 1 Group 95 pm_fxu2
PM_FXU_FIN_GRP95 FXU produced a result 2 Group 95 pm_fxu2
PM_FXLS_FULL_CYC_GRP95 Cycles FXLS queue is full 3 Group 95 pm_fxu2
PM_3INST_CLB_CYC_GRP96 Cycles 3 instructions in CLB 0 Group 96 pm_fxu3
PM_4INST_CLB_CYC_GRP96 Cycles 4 instructions in CLB 1 Group 96 pm_fxu3
PM_FXU0_FIN_GRP96 FXU0 produced a result 2 Group 96 pm_fxu3
PM_FXU1_FIN_GRP96 FXU1 produced a result 3 Group 96 pm_fxu3
PM_THRD_PRIO_4_CYC_GRP97 Cycles thread running at priority level 4 0 Group 97 pm_smt_priorities1
PM_THRD_PRIO_7_CYC_GRP97 Cycles thread running at priority level 7 1 Group 97 pm_smt_priorities1
PM_THRD_PRIO_DIFF_0_CYC_GRP97 Cycles no thread priority difference 2 Group 97 pm_smt_priorities1
PM_THRD_PRIO_DIFF_1or2_CYC_GRP97 Cycles thread priority difference is 1 or 2 3 Group 97 pm_smt_priorities1
PM_THRD_PRIO_3_CYC_GRP98 Cycles thread running at priority level 3 0 Group 98 pm_smt_priorities2
PM_THRD_PRIO_6_CYC_GRP98 Cycles thread running at priority level 6 1 Group 98 pm_smt_priorities2
PM_THRD_PRIO_DIFF_3or4_CYC_GRP98 Cycles thread priority difference is 3 or 4 2 Group 98 pm_smt_priorities2
PM_THRD_PRIO_DIFF_5or6_CYC_GRP98 Cycles thread priority difference is 5 or 6 3 Group 98 pm_smt_priorities2
PM_THRD_PRIO_2_CYC_GRP99 Cycles thread running at priority level 2 0 Group 99 pm_smt_priorities3
PM_THRD_PRIO_5_CYC_GRP99 Cycles thread running at priority level 5 1 Group 99 pm_smt_priorities3
PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP99 Cycles thread priority difference is -1 or -2 2 Group 99 pm_smt_priorities3
PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP99 Cycles thread priority difference is -3 or -4 3 Group 99 pm_smt_priorities3
PM_THRD_PRIO_1_CYC_GRP100 Cycles thread running at priority level 1 0 Group 100 pm_smt_priorities4
PM_HV_CYC_GRP100 Hypervisor Cycles 1 Group 100 pm_smt_priorities4
PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP100 Cycles thread priority difference is -5 or -6 2 Group 100 pm_smt_priorities4
PM_IOPS_CMPL_GRP100 Internal operations completed 3 Group 100 pm_smt_priorities4
PM_THRD_ONE_RUN_CYC_GRP101 One of the threads in run cycles 0 Group 101 pm_smt_both
PM_THRD_GRP_CMPL_BOTH_CYC_GRP101 Cycles group completed by both threads 1 Group 101 pm_smt_both
PM_IOPS_CMPL_GRP101 Internal operations completed 2 Group 101 pm_smt_both
PM_THRD_L2MISS_BOTH_CYC_GRP101 Cycles both threads in L2 misses 3 Group 101 pm_smt_both
PM_SNOOP_TLBIE_GRP102 Snoop TLBIE 0 Group 102 pm_smt_selection
PM_IOPS_CMPL_GRP102 Internal operations completed 1 Group 102 pm_smt_selection
PM_THRD_SEL_T0_GRP102 Decode selected thread 0 2 Group 102 pm_smt_selection
PM_THRD_SEL_T1_GRP102 Decode selected thread 1 3 Group 102 pm_smt_selection
PM_IOPS_CMPL_GRP103 Internal operations completed 0 Group 103 pm_smt_selectover1
PM_0INST_CLB_CYC_GRP103 Cycles no instructions in CLB 1 Group 103 pm_smt_selectover1
PM_THRD_SEL_OVER_CLB_EMPTY_GRP103 Thread selection overrides caused by CLB empty 2 Group 103 pm_smt_selectover1
PM_THRD_SEL_OVER_GCT_IMBAL_GRP103 Thread selection overrides caused by GCT imbalance 3 Group 103 pm_smt_selectover1
PM_IOPS_CMPL_GRP104 Internal operations completed 0 Group 104 pm_smt_selectover2
PM_CYC_GRP104 Processor cycles 1 Group 104 pm_smt_selectover2
PM_THRD_SEL_OVER_ISU_HOLD_GRP104 Thread selection overrides caused by ISU holds 2 Group 104 pm_smt_selectover2
PM_THRD_SEL_OVER_L2MISS_GRP104 Thread selection overrides caused by L2 misses 3 Group 104 pm_smt_selectover2
PM_FAB_CMD_ISSUED_GRP105 Fabric command issued 0 Group 105 pm_fabric1
PM_FAB_DCLAIM_ISSUED_GRP105 dclaim issued 1 Group 105 pm_fabric1
PM_FAB_CMD_RETRIED_GRP105 Fabric command retried 2 Group 105 pm_fabric1
PM_FAB_DCLAIM_RETRIED_GRP105 dclaim retried 3 Group 105 pm_fabric1
PM_FAB_P1toM1_SIDECAR_EMPTY_GRP106 P1 to M1 sidecar empty 0 Group 106 pm_fabric2
PM_FAB_HOLDtoVN_EMPTY_GRP106 Hold buffer to VN empty 1 Group 106 pm_fabric2
PM_FAB_P1toVNorNN_SIDECAR_EMPTY_GRP106 P1 to VN/NN sidecar empty 2 Group 106 pm_fabric2
PM_FAB_VBYPASS_EMPTY_GRP106 Vertical bypass buffer empty 3 Group 106 pm_fabric2
PM_FAB_PNtoNN_DIRECT_GRP107 PN to NN beat went straight to its destination 0 Group 107 pm_fabric3
PM_FAB_PNtoVN_DIRECT_GRP107 PN to VN beat went straight to its destination 1 Group 107 pm_fabric3
PM_FAB_PNtoNN_SIDECAR_GRP107 PN to NN beat went to sidecar first 2 Group 107 pm_fabric3
PM_FAB_PNtoVN_SIDECAR_GRP107 PN to VN beat went to sidecar first 3 Group 107 pm_fabric3
PM_FAB_M1toP1_SIDECAR_EMPTY_GRP108 M1 to P1 sidecar empty 0 Group 108 pm_fabric4
PM_FAB_HOLDtoNN_EMPTY_GRP108 Hold buffer to NN empty 1 Group 108 pm_fabric4
PM_EE_OFF_GRP108 Cycles MSR(EE) bit off 2 Group 108 pm_fabric4
PM_FAB_M1toVNorNN_SIDECAR_EMPTY_GRP108 M1 to VN/NN sidecar empty 3 Group 108 pm_fabric4
PM_SNOOP_RD_RETRY_QFULL_GRP109 Snoop read retry due to read queue full 0 Group 109 pm_snoop1
PM_SNOOP_DCLAIM_RETRY_QFULL_GRP109 Snoop dclaim/flush retry due to write/dclaim queues full 1 Group 109 pm_snoop1
PM_SNOOP_WR_RETRY_QFULL_GRP109 Snoop read retry due to read queue full 2 Group 109 pm_snoop1
PM_SNOOP_PARTIAL_RTRY_QFULL_GRP109 Snoop partial write retry due to partial-write queues full 3 Group 109 pm_snoop1
PM_SNOOP_RD_RETRY_RQ_GRP110 Snoop read retry due to collision with active read queue 0 Group 110 pm_snoop2
PM_SNOOP_RETRY_1AHEAD_GRP110 Snoop retry due to one ahead collision 1 Group 110 pm_snoop2
PM_SNOOP_RD_RETRY_WQ_GRP110 Snoop read retry due to collision with active write queue 2 Group 110 pm_snoop2
PM_IOPS_CMPL_GRP110 Internal operations completed 3 Group 110 pm_snoop2
PM_SNOOP_WR_RETRY_RQ_GRP111 Snoop write/dclaim retry due to collision with active read queue 0 Group 111 pm_snoop3
PM_MEM_HI_PRIO_WR_CMPL_GRP111 High priority write completed 1 Group 111 pm_snoop3
PM_SNOOP_WR_RETRY_WQ_GRP111 Snoop write/dclaim retry due to collision with active write queue 2 Group 111 pm_snoop3
PM_MEM_LO_PRIO_WR_CMPL_GRP111 Low priority write completed 3 Group 111 pm_snoop3
PM_SNOOP_PW_RETRY_RQ_GRP112 Snoop partial-write retry due to collision with active read queue 0 Group 112 pm_snoop4
PM_MEM_RQ_DISP_Q16to19_GRP112 Memory read queue dispatched to queues 16-19 1 Group 112 pm_snoop4
PM_SNOOP_PW_RETRY_WQ_PWQ_GRP112 Snoop partial-write retry due to collision with active write or partial-write queue 2 Group 112 pm_snoop4
PM_SNOOP_PW_RETRY_RQ_GRP112 Snoop partial-write retry due to collision with active read queue 3 Group 112 pm_snoop4
PM_MEM_RQ_DISP_GRP113 Memory read queue dispatched 0 Group 113 pm_mem_rq
PM_MEM_SPEC_RD_CANCEL_GRP113 Speculative memory read cancelled 1 Group 113 pm_mem_rq
PM_MEM_NONSPEC_RD_CANCEL_GRP113 Non speculative memory read cancelled 2 Group 113 pm_mem_rq
PM_EE_OFF_EXT_INT_GRP113 Cycles MSR(EE) bit off and external interrupt pending 3 Group 113 pm_mem_rq
PM_MEM_RQ_DISP_Q0to3_GRP114 Memory read queue dispatched to queues 0-3 0 Group 114 pm_mem_read
PM_MEM_RQ_DISP_Q8to11_GRP114 Memory read queue dispatched to queues 8-11 1 Group 114 pm_mem_read
PM_MEM_RQ_DISP_Q4to7_GRP114 Memory read queue dispatched to queues 4-7 2 Group 114 pm_mem_read
PM_EXT_INT_GRP114 External interrupts 3 Group 114 pm_mem_read
PM_MEM_WQ_DISP_WRITE_GRP115 Memory write queue dispatched due to write 0 Group 115 pm_mem_wq
PM_MEM_WQ_DISP_Q0to7_GRP115 Memory write queue dispatched to queues 0-7 1 Group 115 pm_mem_wq
PM_MEM_WQ_DISP_DCLAIM_GRP115 Memory write queue dispatched due to dclaim/flush 2 Group 115 pm_mem_wq
PM_MEM_WQ_DISP_Q8to15_GRP115 Memory write queue dispatched to queues 8-15 3 Group 115 pm_mem_wq
PM_MEM_PWQ_DISP_GRP116 Memory partial-write queue dispatched 0 Group 116 pm_mem_pwq
PM_MEM_PW_CMPL_GRP116 Memory partial-write completed 1 Group 116 pm_mem_pwq
PM_MEM_PW_GATH_GRP116 Memory partial-write gathered 2 Group 116 pm_mem_pwq
PM_MEM_PWQ_DISP_Q2or3_GRP116 Memory partial-write queue dispatched to Write Queue 2 or 3 3 Group 116 pm_mem_pwq
PM_MRK_GRP_DISP_GRP117 Marked group dispatched 0 Group 117 pm_threshold
PM_MRK_IMR_RELOAD_GRP117 Marked IMR reloaded 1 Group 117 pm_threshold
PM_THRESH_TIMEO_GRP117 Threshold timeout 2 Group 117 pm_threshold
PM_MRK_LSU_FIN_GRP117 Marked instruction LSU processing finished 3 Group 117 pm_threshold
PM_MRK_GRP_DISP_GRP118 Marked group dispatched 0 Group 118 pm_mrk_grp1
PM_MRK_ST_MISS_L1_GRP118 Marked L1 D cache store misses 1 Group 118 pm_mrk_grp1
PM_MRK_INST_FIN_GRP118 Marked instruction finished 2 Group 118 pm_mrk_grp1
PM_MRK_GRP_CMPL_GRP118 Marked group completed 3 Group 118 pm_mrk_grp1
PM_MRK_GRP_ISSUED_GRP119 Marked group issued 0 Group 119 pm_mrk_grp2
PM_MRK_BRU_FIN_GRP119 Marked instruction BRU processing finished 1 Group 119 pm_mrk_grp2
PM_MRK_L1_RELOAD_VALID_GRP119 Marked L1 reload data source valid 2 Group 119 pm_mrk_grp2
PM_MRK_GRP_IC_MISS_GRP119 Group experienced marked I cache miss 3 Group 119 pm_mrk_grp2
PM_MRK_DATA_FROM_L2_GRP120 Marked data loaded from L2 0 Group 120 pm_mrk_dsource1
PM_MRK_DATA_FROM_L2_CYC_GRP120 Marked load latency from L2 1 Group 120 pm_mrk_dsource1
PM_MRK_DATA_FROM_L25_MOD_GRP120 Marked data loaded from L2.5 modified 2 Group 120 pm_mrk_dsource1
PM_MRK_DATA_FROM_L25_MOD_CYC_GRP120 Marked load latency from L2.5 modified 3 Group 120 pm_mrk_dsource1
PM_MRK_DATA_FROM_L25_SHR_GRP121 Marked data loaded from L2.5 shared 0 Group 121 pm_mrk_dsource2
PM_MRK_DATA_FROM_L25_SHR_CYC_GRP121 Marked load latency from L2.5 shared 1 Group 121 pm_mrk_dsource2
PM_IOPS_CMPL_GRP121 Internal operations completed 2 Group 121 pm_mrk_dsource2
PM_FPU_FIN_GRP121 FPU produced a result 3 Group 121 pm_mrk_dsource2
PM_MRK_DATA_FROM_L3_GRP122 Marked data loaded from L3 0 Group 122 pm_mrk_dsource3
PM_MRK_DATA_FROM_L3_CYC_GRP122 Marked load latency from L3 1 Group 122 pm_mrk_dsource3
PM_MRK_DATA_FROM_L35_MOD_GRP122 Marked data loaded from L3.5 modified 2 Group 122 pm_mrk_dsource3
PM_MRK_DATA_FROM_L35_MOD_CYC_GRP122 Marked load latency from L3.5 modified 3 Group 122 pm_mrk_dsource3
PM_MRK_DATA_FROM_RMEM_GRP123 Marked data loaded from remote memory 0 Group 123 pm_mrk_dsource4
PM_MRK_DATA_FROM_L275_SHR_CYC_GRP123 Marked load latency from L2.75 shared 1 Group 123 pm_mrk_dsource4
PM_MRK_DATA_FROM_L275_SHR_GRP123 Marked data loaded from L2.75 shared 2 Group 123 pm_mrk_dsource4
PM_MRK_DATA_FROM_RMEM_CYC_GRP123 Marked load latency from remote memory 3 Group 123 pm_mrk_dsource4
PM_MRK_DATA_FROM_L35_SHR_GRP124 Marked data loaded from L3.5 shared 0 Group 124 pm_mrk_dsource5
PM_MRK_DATA_FROM_L35_SHR_CYC_GRP124 Marked load latency from L3.5 shared 1 Group 124 pm_mrk_dsource5
PM_MRK_DATA_FROM_LMEM_GRP124 Marked data loaded from local memory 2 Group 124 pm_mrk_dsource5
PM_MRK_DATA_FROM_LMEM_CYC_GRP124 Marked load latency from local memory 3 Group 124 pm_mrk_dsource5
PM_MRK_DATA_FROM_L275_MOD_GRP125 Marked data loaded from L2.75 modified 0 Group 125 pm_mrk_dsource6
PM_MRK_DATA_FROM_L275_SHR_CYC_GRP125 Marked load latency from L2.75 shared 1 Group 125 pm_mrk_dsource6
PM_IOPS_CMPL_GRP125 Internal operations completed 2 Group 125 pm_mrk_dsource6
PM_MRK_DATA_FROM_L275_MOD_CYC_GRP125 Marked load latency from L2.75 modified 3 Group 125 pm_mrk_dsource6
PM_MRK_DATA_FROM_L375_MOD_GRP126 Marked data loaded from L3.75 modified 0 Group 126 pm_mrk_dsource7
PM_MRK_DATA_FROM_L375_SHR_CYC_GRP126 Marked load latency from L3.75 shared 1 Group 126 pm_mrk_dsource7
PM_MRK_DATA_FROM_L375_SHR_GRP126 Marked data loaded from L3.75 shared 2 Group 126 pm_mrk_dsource7
PM_MRK_DATA_FROM_L375_MOD_CYC_GRP126 Marked load latency from L3.75 modified 3 Group 126 pm_mrk_dsource7
PM_MRK_DTLB_REF_4K_GRP127 Marked Data TLB reference for 4K page 0 Group 127 pm_mrk_dtlbref
PM_MRK_DTLB_REF_64K_GRP127 Marked Data TLB reference for 64K page 1 Group 127 pm_mrk_dtlbref
PM_MRK_DTLB_REF_16M_GRP127 Marked Data TLB reference for 16M page 2 Group 127 pm_mrk_dtlbref
PM_MRK_DTLB_REF_16G_GRP127 Marked Data TLB reference for 16G page 3 Group 127 pm_mrk_dtlbref
PM_MRK_DTLB_MISS_4K_GRP128 Marked Data TLB misses for 4K page 0 Group 128 pm_mrk_dtlbmiss
PM_MRK_DTLB_MISS_64K_GRP128 Marked Data TLB misses for 64K page 1 Group 128 pm_mrk_dtlbmiss
PM_MRK_DTLB_MISS_16M_GRP128 Marked Data TLB misses for 16M page 2 Group 128 pm_mrk_dtlbmiss
PM_MRK_DTLB_MISS_16G_GRP128 Marked Data TLB misses for 16G page 3 Group 128 pm_mrk_dtlbmiss
PM_MRK_DTLB_REF_GRP129 Marked Data TLB reference 0 Group 129 pm_mrk_dtlb_dslb
PM_MRK_DTLB_MISS_GRP129 Marked Data TLB misses 1 Group 129 pm_mrk_dtlb_dslb
PM_MRK_DSLB_MISS_GRP129 Marked Data SLB misses 2 Group 129 pm_mrk_dtlb_dslb
PM_CYC_GRP129 Processor cycles 3 Group 129 pm_mrk_dtlb_dslb
PM_MRK_DTLB_REF_4K_GRP130 Marked Data TLB reference for 4K page 0 Group 130 pm_mrk_lbref
PM_IOPS_CMPL_GRP130 Internal operations completed 1 Group 130 pm_mrk_lbref
PM_MRK_DTLB_REF_16M_GRP130 Marked Data TLB reference for 16M page 2 Group 130 pm_mrk_lbref
PM_MRK_DSLB_MISS_GRP130 Marked Data SLB misses 3 Group 130 pm_mrk_lbref
PM_MRK_LD_MISS_L1_GRP131 Marked L1 D cache load misses 0 Group 131 pm_mrk_lsmiss
PM_IOPS_CMPL_GRP131 Internal operations completed 1 Group 131 pm_mrk_lsmiss
PM_MRK_ST_CMPL_INT_GRP131 Marked store completed with intervention 2 Group 131 pm_mrk_lsmiss
PM_MRK_CRU_FIN_GRP131 Marked instruction CRU processing finished 3 Group 131 pm_mrk_lsmiss
PM_MRK_ST_CMPL_GRP132 Marked store instruction completed 0 Group 132 pm_mrk_ulsflush
PM_MRK_ST_MISS_L1_GRP132 Marked L1 D cache store misses 1 Group 132 pm_mrk_ulsflush
PM_MRK_LSU_FLUSH_UST_GRP132 Marked unaligned store flushes 2 Group 132 pm_mrk_ulsflush
PM_MRK_LSU_FLUSH_ULD_GRP132 Marked unaligned load flushes 3 Group 132 pm_mrk_ulsflush
PM_MRK_STCX_FAIL_GRP133 Marked STCX failed 0 Group 133 pm_mrk_misc
PM_MRK_ST_GPS_GRP133 Marked store sent to GPS 1 Group 133 pm_mrk_misc
PM_MRK_FPU_FIN_GRP133 Marked instruction FPU processing finished 2 Group 133 pm_mrk_misc
PM_MRK_GRP_TIMEO_GRP133 Marked group completion timeout 3 Group 133 pm_mrk_misc
PM_DATA_FROM_L2_GRP134 Data loaded from L2 0 Group 134 pm_lsref_L1
PM_INST_FROM_L1_GRP134 Instruction fetched from L1 1 Group 134 pm_lsref_L1
PM_ST_REF_L1_GRP134 L1 D cache store references 2 Group 134 pm_lsref_L1
PM_LD_REF_L1_GRP134 L1 D cache load references 3 Group 134 pm_lsref_L1
PM_DATA_FROM_L3_GRP135 Data loaded from L3 0 Group 135 pm_lsref_L2L3
PM_DATA_FROM_LMEM_GRP135 Data loaded from local memory 1 Group 135 pm_lsref_L2L3
PM_ST_REF_L1_GRP135 L1 D cache store references 2 Group 135 pm_lsref_L2L3
PM_LD_REF_L1_GRP135 L1 D cache load references 3 Group 135 pm_lsref_L2L3
PM_ITLB_MISS_GRP136 Instruction TLB misses 0 Group 136 pm_lsref_tlbmiss
PM_DTLB_MISS_GRP136 Data TLB misses 1 Group 136 pm_lsref_tlbmiss
PM_ST_REF_L1_GRP136 L1 D cache store references 2 Group 136 pm_lsref_tlbmiss
PM_LD_REF_L1_GRP136 L1 D cache load references 3 Group 136 pm_lsref_tlbmiss
PM_DATA_FROM_L3_GRP137 Data loaded from L3 0 Group 137 pm_Dmiss
PM_DATA_FROM_LMEM_GRP137 Data loaded from local memory 1 Group 137 pm_Dmiss
PM_LD_MISS_L1_GRP137 L1 D cache load misses 2 Group 137 pm_Dmiss
PM_ST_MISS_L1_GRP137 L1 D cache store misses 3 Group 137 pm_Dmiss
PM_CYC_GRP138 Processor cycles 0 Group 138 pm_prefetchX
PM_IC_PREF_REQ_GRP138 Instruction prefetch requests 1 Group 138 pm_prefetchX
PM_L1_PREF_GRP138 L1 cache data prefetches 2 Group 138 pm_prefetchX
PM_L2_PREF_GRP138 L2 cache prefetches 3 Group 138 pm_prefetchX
PM_BR_UNCOND_GRP139 Unconditional branch 0 Group 139 pm_branchX
PM_BR_PRED_TA_GRP139 A conditional branch was predicted, target prediction 1 Group 139 pm_branchX
PM_BR_PRED_CR_GRP139 A conditional branch was predicted, CR prediction 2 Group 139 pm_branchX
PM_BR_ISSUED_GRP139 Branches issued 3 Group 139 pm_branchX
PM_FPU0_STALL3_GRP140 FPU0 stalled in pipe3 0 Group 140 pm_fpuX1
PM_FPU1_STALL3_GRP140 FPU1 stalled in pipe3 1 Group 140 pm_fpuX1
PM_FPU0_FIN_GRP140 FPU0 produced a result 2 Group 140 pm_fpuX1
PM_FPU0_FPSCR_GRP140 FPU0 executed FPSCR instruction 3 Group 140 pm_fpuX1
PM_FPU0_FMA_GRP141 FPU0 executed multiply-add instruction 0 Group 141 pm_fpuX2
PM_FPU1_FMA_GRP141 FPU1 executed multiply-add instruction 1 Group 141 pm_fpuX2
PM_FPU0_FRSP_FCONV_GRP141 FPU0 executed FRSP or FCONV instructions 2 Group 141 pm_fpuX2
PM_FPU1_FRSP_FCONV_GRP141 FPU1 executed FRSP or FCONV instructions 3 Group 141 pm_fpuX2
PM_FPU0_1FLOP_GRP142 FPU0 executed add, mult, sub, cmp or sel instruction 0 Group 142 pm_fpuX3
PM_FPU1_1FLOP_GRP142 FPU1 executed add, mult, sub, cmp or sel instruction 1 Group 142 pm_fpuX3
PM_FPU0_FIN_GRP142 FPU0 produced a result 2 Group 142 pm_fpuX3
PM_FPU1_FIN_GRP142 FPU1 produced a result 3 Group 142 pm_fpuX3
PM_FPU_1FLOP_GRP143 FPU executed one flop instruction 0 Group 143 pm_fpuX4
PM_FPU_FMA_GRP143 FPU executed multiply-add instruction 1 Group 143 pm_fpuX4
PM_ST_REF_L1_GRP143 L1 D cache store references 2 Group 143 pm_fpuX4
PM_LD_REF_L1_GRP143 L1 D cache load references 3 Group 143 pm_fpuX4
PM_FPU_SINGLE_GRP144 FPU executed single precision instruction 0 Group 144 pm_fpuX5
PM_FPU_STF_GRP144 FPU executed store instruction 1 Group 144 pm_fpuX5
PM_FPU0_FIN_GRP144 FPU0 produced a result 2 Group 144 pm_fpuX5
PM_FPU1_FIN_GRP144 FPU1 produced a result 3 Group 144 pm_fpuX5
PM_FPU_FDIV_GRP145 FPU executed FDIV instruction 0 Group 145 pm_fpuX6
PM_FPU_FSQRT_GRP145 FPU executed FSQRT instruction 1 Group 145 pm_fpuX6
PM_FPU_FRSP_FCONV_GRP145 FPU executed FRSP or FCONV instructions 2 Group 145 pm_fpuX6
PM_FPU_FIN_GRP145 FPU produced a result 3 Group 145 pm_fpuX6
PM_FPU_1FLOP_GRP146 FPU executed one flop instruction 0 Group 146 pm_fpuX7
PM_FPU_FMA_GRP146 FPU executed multiply-add instruction 1 Group 146 pm_fpuX7
PM_FPU_STF_GRP146 FPU executed store instruction 2 Group 146 pm_fpuX7
PM_FPU_FIN_GRP146 FPU produced a result 3 Group 146 pm_fpuX7
PM_CYC_GRP147 Processor cycles 0 Group 147 pm_hpmcount8
PM_MRK_FXU_FIN_GRP147 Marked instruction FXU processing finished 1 Group 147 pm_hpmcount8
PM_CYC_GRP147 Processor cycles 2 Group 147 pm_hpmcount8
PM_FPU_FIN_GRP147 FPU produced a result 3 Group 147 pm_hpmcount8
PM_INST_CMPL_GRP148 Instructions completed 0 Group 148 pm_hpmcount2
PM_FPU_STF_GRP148 FPU executed store instruction 1 Group 148 pm_hpmcount2
PM_INST_DISP_GRP148 Instructions dispatched 2 Group 148 pm_hpmcount2
PM_LSU_LDF_GRP148 LSU executed Floating Point load instruction 3 Group 148 pm_hpmcount2
PM_CYC_GRP149 Processor cycles 0 Group 149 pm_hpmcount3
PM_INST_DISP_ATTEMPT_GRP149 Instructions dispatch attempted 1 Group 149 pm_hpmcount3
PM_LD_MISS_L1_GRP149 L1 D cache load misses 2 Group 149 pm_hpmcount3
PM_ST_MISS_L1_GRP149 L1 D cache store misses 3 Group 149 pm_hpmcount3
PM_TLB_MISS_GRP150 TLB misses 0 Group 150 pm_hpmcount4
PM_CYC_GRP150 Processor cycles 1 Group 150 pm_hpmcount4
PM_ST_REF_L1_GRP150 L1 D cache store references 2 Group 150 pm_hpmcount4
PM_LD_REF_L1_GRP150 L1 D cache load references 3 Group 150 pm_hpmcount4
PM_FPU_FDIV_GRP151 FPU executed FDIV instruction 0 Group 151 pm_flop
PM_FPU_FMA_GRP151 FPU executed multiply-add instruction 1 Group 151 pm_flop
PM_FPU_FSQRT_GRP151 FPU executed FSQRT instruction 2 Group 151 pm_flop
PM_FPU_1FLOP_GRP151 FPU executed one flop instruction 3 Group 151 pm_flop
PM_INST_CMPL_GRP152 Instructions completed 0 Group 152 pm_eprof1
PM_CYC_GRP152 Processor cycles 1 Group 152 pm_eprof1
PM_LD_MISS_L1_GRP152 L1 D cache load misses 2 Group 152 pm_eprof1
PM_DC_INV_L2_GRP152 L1 D cache entries invalidated from L2 3 Group 152 pm_eprof1
PM_INST_CMPL_GRP153 Instructions completed 0 Group 153 pm_eprof2
PM_ST_REF_L1_GRP153 L1 D cache store references 1 Group 153 pm_eprof2
PM_INST_DISP_GRP153 Instructions dispatched 2 Group 153 pm_eprof2
PM_LD_REF_L1_GRP153 L1 D cache load references 3 Group 153 pm_eprof2
PM_CYC_GRP154 Processor cycles 0 Group 154 pm_flip
PM_FPU_FMA_GRP154 FPU executed multiply-add instruction 1 Group 154 pm_flip
PM_FPU_STF_GRP154 FPU executed store instruction 2 Group 154 pm_flip
PM_FPU_FIN_GRP154 FPU produced a result 3 Group 154 pm_flip
PM_CYC_GRP155 Processor cycles 0 Group 155 pm_hpmcount5
PM_DTLB_MISS_GRP155 Data TLB misses 1 Group 155 pm_hpmcount5
PM_LD_MISS_L1_GRP155 L1 D cache load misses 2 Group 155 pm_hpmcount5
PM_LD_REF_L1_GRP155 L1 D cache load references 3 Group 155 pm_hpmcount5
PM_CYC_GRP156 Processor cycles 0 Group 156 pm_hpmcount6
PM_INST_CMPL_GRP156 Instructions completed 1 Group 156 pm_hpmcount6
PM_ST_REF_L1_GRP156 L1 D cache store references 2 Group 156 pm_hpmcount6
PM_ST_MISS_L1_GRP156 L1 D cache store misses 3 Group 156 pm_hpmcount6
PM_INST_CMPL_GRP157 Instructions completed 0 Group 157 pm_hpmcount7
PM_DATA_FROM_LMEM_GRP157 Data loaded from local memory 1 Group 157 pm_hpmcount7
PM_CYC_GRP157 Processor cycles 2 Group 157 pm_hpmcount7
PM_DATA_FROM_RMEM_GRP157 Data loaded from remote memory 3 Group 157 pm_hpmcount7
PM_MRK_GRP_DISP_GRP158 Marked group dispatched 0 Group 158 pm_ep_threshold
PM_INST_CMPL_GRP158 Instructions completed 1 Group 158 pm_ep_threshold
PM_THRESH_TIMEO_GRP158 Threshold timeout 2 Group 158 pm_ep_threshold
PM_MRK_LSU_FIN_GRP158 Marked instruction LSU processing finished 3 Group 158 pm_ep_threshold
PM_MRK_GRP_DISP_GRP159 Marked group dispatched 0 Group 159 pm_ep_mrk_grp1
PM_INST_CMPL_GRP159 Instructions completed 1 Group 159 pm_ep_mrk_grp1
PM_MRK_INST_FIN_GRP159 Marked instruction finished 2 Group 159 pm_ep_mrk_grp1
PM_MRK_GRP_CMPL_GRP159 Marked group completed 3 Group 159 pm_ep_mrk_grp1
PM_MRK_GRP_ISSUED_GRP160 Marked group issued 0 Group 160 pm_ep_mrk_grp2
PM_INST_CMPL_GRP160 Instructions completed 1 Group 160 pm_ep_mrk_grp2
PM_MRK_L1_RELOAD_VALID_GRP160 Marked L1 reload data source valid 2 Group 160 pm_ep_mrk_grp2
PM_MRK_GRP_IC_MISS_GRP160 Group experienced marked I cache miss 3 Group 160 pm_ep_mrk_grp2
PM_MRK_DATA_FROM_L2_GRP161 Marked data loaded from L2 0 Group 161 pm_ep_mrk_dsource1
PM_INST_CMPL_GRP161 Instructions completed 1 Group 161 pm_ep_mrk_dsource1
PM_MRK_DATA_FROM_L25_MOD_GRP161 Marked data loaded from L2.5 modified 2 Group 161 pm_ep_mrk_dsource1
PM_MRK_DATA_FROM_L25_MOD_CYC_GRP161 Marked load latency from L2.5 modified 3 Group 161 pm_ep_mrk_dsource1
PM_MRK_DATA_FROM_L25_SHR_GRP162 Marked data loaded from L2.5 shared 0 Group 162 pm_ep_mrk_dsource2
PM_INST_CMPL_GRP162 Instructions completed 1 Group 162 pm_ep_mrk_dsource2
PM_MRK_IMR_RELOAD_GRP162 Marked IMR reloaded 2 Group 162 pm_ep_mrk_dsource2
PM_FPU_FIN_GRP162 FPU produced a result 3 Group 162 pm_ep_mrk_dsource2
PM_INST_CMPL_GRP163 Instructions completed 0 Group 163 pm_ep_mrk_dsource3
PM_MRK_DATA_FROM_L3_CYC_GRP163 Marked load latency from L3 1 Group 163 pm_ep_mrk_dsource3
PM_MRK_DATA_FROM_L35_MOD_GRP163 Marked data loaded from L3.5 modified 2 Group 163 pm_ep_mrk_dsource3
PM_MRK_DATA_FROM_L35_MOD_CYC_GRP163 Marked load latency from L3.5 modified 3 Group 163 pm_ep_mrk_dsource3
PM_INST_CMPL_GRP164 Instructions completed 0 Group 164 pm_ep_mrk_dsource4
PM_MRK_DATA_FROM_L275_SHR_CYC_GRP164 Marked load latency from L2.75 shared 1 Group 164 pm_ep_mrk_dsource4
PM_MRK_DATA_FROM_L275_SHR_GRP164 Marked data loaded from L2.75 shared 2 Group 164 pm_ep_mrk_dsource4
PM_MRK_DATA_FROM_RMEM_CYC_GRP164 Marked load latency from remote memory 3 Group 164 pm_ep_mrk_dsource4
PM_MRK_DATA_FROM_L35_SHR_GRP165 Marked data loaded from L3.5 shared 0 Group 165 pm_ep_mrk_dsource5
PM_INST_CMPL_GRP165 Instructions completed 1 Group 165 pm_ep_mrk_dsource5
PM_MRK_DATA_FROM_LMEM_GRP165 Marked data loaded from local memory 2 Group 165 pm_ep_mrk_dsource5
PM_MRK_DATA_FROM_LMEM_CYC_GRP165 Marked load latency from local memory 3 Group 165 pm_ep_mrk_dsource5
PM_INST_CMPL_GRP166 Instructions completed 0 Group 166 pm_ep_mrk_dsource6
PM_MRK_DATA_FROM_L275_SHR_CYC_GRP166 Marked load latency from L2.75 shared 1 Group 166 pm_ep_mrk_dsource6
PM_IOPS_CMPL_GRP166 Internal operations completed 2 Group 166 pm_ep_mrk_dsource6
PM_MRK_DATA_FROM_L275_MOD_CYC_GRP166 Marked load latency from L2.75 modified 3 Group 166 pm_ep_mrk_dsource6
PM_INST_CMPL_GRP167 Instructions completed 0 Group 167 pm_ep_mrk_dsource7
PM_MRK_DATA_FROM_L375_SHR_CYC_GRP167 Marked load latency from L3.75 shared 1 Group 167 pm_ep_mrk_dsource7
PM_MRK_DATA_FROM_L375_SHR_GRP167 Marked data loaded from L3.75 shared 2 Group 167 pm_ep_mrk_dsource7
PM_MRK_DATA_FROM_L375_MOD_CYC_GRP167 Marked load latency from L3.75 modified 3 Group 167 pm_ep_mrk_dsource7
PM_INST_CMPL_GRP168 Instructions completed 0 Group 168 pm_ep_mrk_lbmiss
PM_MRK_DTLB_MISS_64K_GRP168 Marked Data TLB misses for 64K page 1 Group 168 pm_ep_mrk_lbmiss
PM_MRK_DTLB_MISS_16M_GRP168 Marked Data TLB misses for 16M page 2 Group 168 pm_ep_mrk_lbmiss
PM_MRK_DTLB_MISS_16G_GRP168 Marked Data TLB misses for 16G page 3 Group 168 pm_ep_mrk_lbmiss
PM_INST_CMPL_GRP169 Instructions completed 0 Group 169 pm_ep_mrk_dtlbref
PM_MRK_DTLB_REF_64K_GRP169 Marked Data TLB reference for 64K page 1 Group 169 pm_ep_mrk_dtlbref
PM_MRK_DTLB_REF_16M_GRP169 Marked Data TLB reference for 16M page 2 Group 169 pm_ep_mrk_dtlbref
PM_MRK_DTLB_REF_16G_GRP169 Marked Data TLB reference for 16G page 3 Group 169 pm_ep_mrk_dtlbref
PM_INST_CMPL_GRP170 Instructions completed 0 Group 170 pm_ep_mrk_dtlbmiss
PM_MRK_DTLB_MISS_64K_GRP170 Marked Data TLB misses for 64K page 1 Group 170 pm_ep_mrk_dtlbmiss
PM_MRK_DTLB_MISS_16M_GRP170 Marked Data TLB misses for 16M page 2 Group 170 pm_ep_mrk_dtlbmiss
PM_MRK_DTLB_MISS_16G_GRP170 Marked Data TLB misses for 16G page 3 Group 170 pm_ep_mrk_dtlbmiss
PM_MRK_DTLB_REF_4K_GRP171 Marked Data TLB reference for 4K page 0 Group 171 pm_ep_mrk_lbref
PM_INST_CMPL_GRP171 Instructions completed 1 Group 171 pm_ep_mrk_lbref
PM_MRK_DTLB_REF_16M_GRP171 Marked Data TLB reference for 16M page 2 Group 171 pm_ep_mrk_lbref
PM_MRK_DSLB_MISS_GRP171 Marked Data SLB misses 3 Group 171 pm_ep_mrk_lbref
PM_MRK_LD_MISS_L1_GRP172 Marked L1 D cache load misses 0 Group 172 pm_ep_mrk_lsmiss
PM_INST_CMPL_GRP172 Instructions completed 1 Group 172 pm_ep_mrk_lsmiss
PM_MRK_ST_CMPL_INT_GRP172 Marked store completed with intervention 2 Group 172 pm_ep_mrk_lsmiss
PM_MRK_CRU_FIN_GRP172 Marked instruction CRU processing finished 3 Group 172 pm_ep_mrk_lsmiss
PM_MRK_ST_CMPL_GRP173 Marked store instruction completed 0 Group 173 pm_ep_mrk_ulsflush
PM_INST_CMPL_GRP173 Instructions completed 1 Group 173 pm_ep_mrk_ulsflush
PM_MRK_LSU_FLUSH_UST_GRP173 Marked unaligned store flushes 2 Group 173 pm_ep_mrk_ulsflush
PM_MRK_LSU_FLUSH_ULD_GRP173 Marked unaligned load flushes 3 Group 173 pm_ep_mrk_ulsflush
PM_INST_CMPL_GRP174 Instructions completed 0 Group 174 pm_ep_mrk_misc1
PM_MRK_ST_GPS_GRP174 Marked store sent to GPS 1 Group 174 pm_ep_mrk_misc1
PM_MRK_FPU_FIN_GRP174 Marked instruction FPU processing finished 2 Group 174 pm_ep_mrk_misc1
PM_MRK_GRP_TIMEO_GRP174 Marked group completion timeout 3 Group 174 pm_ep_mrk_misc1
PM_INST_CMPL_GRP175 Instructions completed 0 Group 175 pm_ep_mrk_misc2
PM_MRK_DATA_FROM_L25_SHR_CYC_GRP175 Marked load latency from L2.5 shared 1 Group 175 pm_ep_mrk_misc2
PM_MRK_DATA_FROM_L3_GRP175 Marked data loaded from L3 2 Group 175 pm_ep_mrk_misc2
PM_MRK_IMR_RELOAD_GRP175 Marked IMR reloaded 3 Group 175 pm_ep_mrk_misc2
PM_INST_CMPL_GRP176 Instructions completed 0 Group 176 pm_ep_mrk_misc3
PM_MRK_DATA_FROM_L35_SHR_CYC_GRP176 Marked load latency from L3.5 shared 1 Group 176 pm_ep_mrk_misc3
PM_MRK_DTLB_MISS_GRP176 Marked Data TLB misses 2 Group 176 pm_ep_mrk_misc3
PM_MRK_DATA_FROM_RMEM_GRP176 Marked data loaded from remote memory 3 Group 176 pm_ep_mrk_misc3
PM_MRK_DTLB_MISS_4K_GRP177 Marked Data TLB misses for 4K page 0 Group 177 pm_ep_mrk_misc4
PM_INST_CMPL_GRP177 Instructions completed 1 Group 177 pm_ep_mrk_misc4
PM_MRK_DTLB_REF_GRP177 Marked Data TLB reference 2 Group 177 pm_ep_mrk_misc4
PM_MRK_DATA_FROM_L275_MOD_GRP177 Marked data loaded from L2.75 modified 3 Group 177 pm_ep_mrk_misc4
PM_MRK_DTLB_REF_4K_GRP178 Marked Data TLB reference for 4K page 0 Group 178 pm_ep_mrk_misc5
PM_INST_CMPL_GRP178 Instructions completed 1 Group 178 pm_ep_mrk_misc5
PM_IOPS_CMPL_GRP178 Internal operations completed 2 Group 178 pm_ep_mrk_misc5
PM_MRK_LSU0_FLUSH_SRQ_GRP178 LSU0 marked SRQ lhs flushes 3 Group 178 pm_ep_mrk_misc5
PM_MRK_DTLB_MISS_4K_GRP179 Marked Data TLB misses for 4K page 0 Group 179 pm_ep_mrk_misc6
PM_INST_CMPL_GRP179 Instructions completed 1 Group 179 pm_ep_mrk_misc6
PM_MRK_LSU1_FLUSH_ULD_GRP179 LSU1 marked unaligned load flushes 2 Group 179 pm_ep_mrk_misc6
PM_MRK_LSU1_FLUSH_UST_GRP179 LSU1 marked unaligned store flushes 3 Group 179 pm_ep_mrk_misc6
PM_INST_CMPL_GRP180 Instructions completed 0 Group 180 pm_ep_mrk_misc7
PM_MRK_DATA_FROM_L2_CYC_GRP180 Marked load latency from L2 1 Group 180 pm_ep_mrk_misc7
PM_MRK_LSU0_FLUSH_ULD_GRP180 LSU0 marked unaligned load flushes 2 Group 180 pm_ep_mrk_misc7
PM_MRK_LSU0_FLUSH_UST_GRP180 LSU0 marked unaligned store flushes 3 Group 180 pm_ep_mrk_misc7
PM_INST_CMPL_GRP181 Instructions completed 0 Group 181 pm_ep_mrk_misc8
PM_MRK_BRU_FIN_GRP181 Marked instruction BRU processing finished 1 Group 181 pm_ep_mrk_misc8
PM_MRK_LSU0_FLUSH_LRQ_GRP181 LSU0 marked LRQ flushes 2 Group 181 pm_ep_mrk_misc8
PM_MRK_LSU0_FLUSH_SRQ_GRP181 LSU0 marked SRQ lhs flushes 3 Group 181 pm_ep_mrk_misc8
PM_INST_CMPL_GRP182 Instructions completed 0 Group 182 pm_ep_mrk_misc9
PM_MRK_LSU1_FLUSH_LRQ_GRP182 LSU1 marked LRQ flushes 1 Group 182 pm_ep_mrk_misc9
PM_MRK_LSU1_FLUSH_SRQ_GRP182 LSU1 marked SRQ lhs flushes 2 Group 182 pm_ep_mrk_misc9
PM_MRK_STCX_FAIL_GRP182 Marked STCX failed 3 Group 182 pm_ep_mrk_misc9
PM_INST_CMPL_GRP183 Instructions completed 0 Group 183 pm_ep_mrk_misc10
PM_MRK_LD_MISS_L1_LSU0_GRP183 LSU0 marked L1 D cache load misses 1 Group 183 pm_ep_mrk_misc10
PM_MRK_LD_MISS_L1_LSU1_GRP183 LSU1 marked L1 D cache load misses 2 Group 183 pm_ep_mrk_misc10
PM_MRK_ST_MISS_L1_GRP183 Marked L1 D cache store misses 3 Group 183 pm_ep_mrk_misc10
PM_INST_CMPL_GRP184 Instructions completed 0 Group 184 pm_ep_mrk_misc11
PM_MRK_BRU_FIN_GRP184 Marked instruction BRU processing finished 1 Group 184 pm_ep_mrk_misc11
PM_MRK_DATA_FROM_L25_MOD_GRP184 Marked data loaded from L2.5 modified 2 Group 184 pm_ep_mrk_misc11
PM_MRK_DATA_FROM_L375_MOD_GRP184 Marked data loaded from L3.75 modified 3 Group 184 pm_ep_mrk_misc11
PM_INST_CMPL_GRP185 Instructions completed 0 Group 185 pm_ep_mrk_misc12
PM_MRK_LSU_FLUSH_UST_GRP185 Marked unaligned store flushes 1 Group 185 pm_ep_mrk_misc12
PM_MRK_LSU_FLUSH_LRQ_GRP185 Marked LRQ flushes 2 Group 185 pm_ep_mrk_misc12
PM_MRK_LSU_FLUSH_SRQ_GRP185 Marked SRQ lhs flushes 3 Group 185 pm_ep_mrk_misc12
PM_MRK_DATA_FROM_L2_GRP186 Marked data loaded from L2 0 Group 186 pm_ep_mrk_misc13
PM_INST_CMPL_GRP186 Instructions completed 1 Group 186 pm_ep_mrk_misc13
PM_MRK_DATA_FROM_L2MISS_GRP186 Marked data loaded missed L2 2 Group 186 pm_ep_mrk_misc13
PM_MRK_LSU_SRQ_INST_VALID_GRP186 Marked instruction valid in SRQ 3 Group 186 pm_ep_mrk_misc13
PM_INST_CMPL_GRP187 Instructions completed 0 Group 187 pm_ep_mrk_misc14
PM_MRK_FXU_FIN_GRP187 Marked instruction FXU processing finished 1 Group 187 pm_ep_mrk_misc14
PM_MRK_FPU_FIN_GRP187 Marked instruction FPU processing finished 2 Group 187 pm_ep_mrk_misc14
PM_MRK_LSU_FIN_GRP187 Marked instruction LSU processing finished 3 Group 187 pm_ep_mrk_misc14
PM_INST_CMPL_GRP188 Instructions completed 0 Group 188 pm_ep_mrk_misc15
PM_MRK_GRP_BR_REDIR_GRP188 Group experienced marked branch redirect 1 Group 188 pm_ep_mrk_misc15
PM_MRK_INST_FIN_GRP188 Marked instruction finished 2 Group 188 pm_ep_mrk_misc15
PM_MRK_GRP_CMPL_GRP188 Marked group completed 3 Group 188 pm_ep_mrk_misc15
Don't speculate - benchmark. - Dan Bernstein
2014/09/12