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ppc64 POWER6 events

This is a list of all ppc64 POWER6's performance counter event types.

NameDescriptionCounters usableGroup
CYCLES Processor Cycles 3
PM_RUN_CYC_GRP1 Run cycles 0 Group 1 pm_utilization
PM_INST_CMPL_GRP1 Instructions completed 1 Group 1 pm_utilization
PM_INST_DISP_GRP1 Instructions dispatched 2 Group 1 pm_utilization
PM_CYC_GRP1 Processor cycles 3 Group 1 pm_utilization
PM_THRD_ONE_RUN_CYC_GRP2 One of the threads in run cycles 0 Group 2 pm_utilization_capacity
PM_CYC_GRP2 Processor cycles 1 Group 2 pm_utilization_capacity
PM_THRD_CONC_RUN_INST_GRP2 Concurrent run instructions 2 Group 2 pm_utilization_capacity
PM_RUN_PURR_GRP2 Run PURR Event 3 Group 2 pm_utilization_capacity
PM_BR_PRED_CR_GRP3 A conditional branch was predicted, CR prediction 0 Group 3 pm_branch
PM_BR_MPRED_CR_GRP3 Branch mispredictions due to CR bit setting 1 Group 3 pm_branch
PM_BR_PRED_GRP3 A conditional branch was predicted 2 Group 3 pm_branch
PM_BR_MPRED_COUNT_GRP3 Branch misprediction due to count prediction 3 Group 3 pm_branch
PM_BR_PRED_CCACHE_GRP4 Branch count cache prediction 0 Group 4 pm_branch2
PM_BR_PRED_LSTACK_GRP4 A conditional branch was predicted, link stack 1 Group 4 pm_branch2
PM_BR_MPRED_CCACHE_GRP4 Branch misprediction due to count cache prediction 2 Group 4 pm_branch2
PM_BR_MPRED_TA_GRP4 Branch mispredictions due to target address 3 Group 4 pm_branch2
PM_BR_PRED_GRP5 A conditional branch was predicted 0 Group 5 pm_branch3
PM_BR_PRED_CR_GRP5 A conditional branch was predicted, CR prediction 1 Group 5 pm_branch3
PM_BR_PRED_CCACHE_GRP5 Branch count cache prediction 2 Group 5 pm_branch3
PM_BR_PRED_LSTACK_GRP5 A conditional branch was predicted, link stack 3 Group 5 pm_branch3
PM_BR_MPRED_CR_GRP6 Branch mispredictions due to CR bit setting 0 Group 6 pm_branch4
PM_BR_MPRED_COUNT_GRP6 Branch misprediction due to count prediction 1 Group 6 pm_branch4
PM_BR_MPRED_TA_GRP6 Branch mispredictions due to target address 2 Group 6 pm_branch4
PM_BR_MPRED_CCACHE_GRP6 Branch misprediction due to count cache prediction 3 Group 6 pm_branch4
PM_BR_PRED_GRP7 A conditional branch was predicted 0 Group 7 pm_branch5
PM_BR_TAKEN_GRP7 Branches taken 1 Group 7 pm_branch5
PM_BRU_FIN_GRP7 BRU produced a result 2 Group 7 pm_branch5
PM_BR_MPRED_GRP7 Branches incorrectly predicted 3 Group 7 pm_branch5
PM_DATA_FROM_L2_GRP8 Data loaded from L2 0 Group 8 pm_dsource
PM_DATA_FROM_L21_GRP8 Data loaded from private L2 other core 1 Group 8 pm_dsource
PM_DATA_FROM_L2MISS_GRP8 Data loaded missed L2 2 Group 8 pm_dsource
PM_DATA_FROM_L3MISS_GRP8 Data loaded from private L3 miss 3 Group 8 pm_dsource
PM_DATA_FROM_L35_MOD_GRP9 Data loaded from L3.5 modified 0 Group 9 pm_dsource2
PM_DATA_FROM_L35_SHR_GRP9 Data loaded from L3.5 shared 1 Group 9 pm_dsource2
PM_DATA_FROM_L3_GRP9 Data loaded from L3 2 Group 9 pm_dsource2
PM_DATA_FROM_L3MISS_GRP9 Data loaded from private L3 miss 3 Group 9 pm_dsource2
PM_DATA_FROM_L35_MOD_GRP10 Data loaded from L3.5 modified 0 Group 10 pm_dsource3
PM_DATA_FROM_L35_SHR_GRP10 Data loaded from L3.5 shared 1 Group 10 pm_dsource3
PM_DATA_FROM_L25_MOD_GRP10 Data loaded from L2.5 modified 2 Group 10 pm_dsource3
PM_DATA_FROM_L25_SHR_GRP10 Data loaded from L2.5 shared 3 Group 10 pm_dsource3
PM_DATA_FROM_RL2L3_MOD_GRP11 Data loaded from remote L2 or L3 modified 0 Group 11 pm_dsource4
PM_DATA_FROM_RL2L3_SHR_GRP11 Data loaded from remote L2 or L3 shared 1 Group 11 pm_dsource4
PM_DATA_FROM_DL2L3_SHR_GRP11 Data loaded from distant L2 or L3 shared 2 Group 11 pm_dsource4
PM_DATA_FROM_DL2L3_MOD_GRP11 Data loaded from distant L2 or L3 modified 3 Group 11 pm_dsource4
PM_DATA_FROM_MEM_DP_GRP12 Data loaded from double pump memory 0 Group 12 pm_dsource5
PM_DATA_FROM_DMEM_GRP12 Data loaded from distant memory 1 Group 12 pm_dsource5
PM_DATA_FROM_RMEM_GRP12 Data loaded from remote memory 2 Group 12 pm_dsource5
PM_DATA_FROM_LMEM_GRP12 Data loaded from local memory 3 Group 12 pm_dsource5
PM_LD_MISS_L1_CYC_GRP13 L1 data load miss cycles 0 Group 13 pm_dlatencies
PM_DATA_FROM_RL2L3_SHR_CYC_GRP13 Load latency from remote L2 or L3 shared 1 Group 13 pm_dlatencies
PM_CYC_GRP13 Processor cycles 2 Group 13 pm_dlatencies
PM_DATA_FROM_L25_MOD_CYC_GRP13 Load latency from L2.5 modified 3 Group 13 pm_dlatencies
PM_INST_CMPL_GRP14 Instructions completed 0 Group 14 pm_dlatencies2
PM_DATA_FROM_LMEM_CYC_GRP14 Load latency from local memory 1 Group 14 pm_dlatencies2
PM_CYC_GRP14 Processor cycles 2 Group 14 pm_dlatencies2
PM_DATA_FROM_DL2L3_MOD_CYC_GRP14 Load latency from distant L2 or L3 modified 3 Group 14 pm_dlatencies2
PM_INST_CMPL_GRP15 Instructions completed 0 Group 15 pm_dlatencies3
PM_DATA_FROM_DMEM_CYC_GRP15 Load latency from distant memory 1 Group 15 pm_dlatencies3
PM_DATA_FROM_RMEM_GRP15 Data loaded from remote memory 2 Group 15 pm_dlatencies3
PM_DATA_FROM_RMEM_CYC_GRP15 Load latency from remote memory 3 Group 15 pm_dlatencies3
PM_DATA_FROM_L35_MOD_GRP16 Data loaded from L3.5 modified 0 Group 16 pm_dlatencies4
PM_DATA_FROM_DL2L3_SHR_CYC_GRP16 Load latency from distant L2 or L3 shared 1 Group 16 pm_dlatencies4
PM_DATA_FROM_DL2L3_SHR_GRP16 Data loaded from distant L2 or L3 shared 2 Group 16 pm_dlatencies4
PM_DATA_FROM_L35_MOD_CYC_GRP16 Load latency from L3.5 modified 3 Group 16 pm_dlatencies4
PM_DATA_FROM_RL2L3_MOD_GRP17 Data loaded from remote L2 or L3 modified 0 Group 17 pm_dlatencies5
PM_DATA_FROM_L3_CYC_GRP17 Load latency from L3 1 Group 17 pm_dlatencies5
PM_DATA_FROM_L3_GRP17 Data loaded from L3 2 Group 17 pm_dlatencies5
PM_DATA_FROM_RL2L3_MOD_CYC_GRP17 Load latency from remote L2 or L3 modified 3 Group 17 pm_dlatencies5
PM_DATA_FROM_MEM_DP_GRP18 Data loaded from double pump memory 0 Group 18 pm_dlatencies6
PM_DATA_FROM_L25_SHR_CYC_GRP18 Load latency from L2.5 shared 1 Group 18 pm_dlatencies6
PM_DATA_FROM_L25_MOD_GRP18 Data loaded from L2.5 modified 2 Group 18 pm_dlatencies6
PM_DATA_FROM_MEM_DP_CYC_GRP18 Load latency from double pump memory 3 Group 18 pm_dlatencies6
PM_DATA_FROM_L2_GRP19 Data loaded from L2 0 Group 19 pm_dlatencies7
PM_DATA_FROM_L2_CYC_GRP19 Load latency from L2 1 Group 19 pm_dlatencies7
PM_INST_DISP_GRP19 Instructions dispatched 2 Group 19 pm_dlatencies7
PM_L1_DCACHE_RELOAD_VALID_GRP19 L1 reload data source valid 3 Group 19 pm_dlatencies7
PM_FLUSH_GRP20 Flushes 0 Group 20 pm_dlatencies8
PM_DATA_FROM_L21_GRP20 Data loaded from private L2 other core 1 Group 20 pm_dlatencies8
PM_CYC_GRP20 Processor cycles 2 Group 20 pm_dlatencies8
PM_DATA_FROM_L21_CYC_GRP20 Load latency from private L2 other core 3 Group 20 pm_dlatencies8
PM_1PLUS_PPC_DISP_GRP21 Cycles at least one instruction dispatched 0 Group 21 pm_dlatencies9
PM_DATA_FROM_LMEM_CYC_GRP21 Load latency from local memory 1 Group 21 pm_dlatencies9
PM_INST_DISP_GRP21 Instructions dispatched 2 Group 21 pm_dlatencies9
PM_DATA_FROM_LMEM_GRP21 Data loaded from local memory 3 Group 21 pm_dlatencies9
PM_DATA_FROM_L35_MOD_GRP22 Data loaded from L3.5 modified 0 Group 22 pm_dlatencies10
PM_DATA_FROM_L35_SHR_CYC_GRP22 Load latency from L3.5 shared 1 Group 22 pm_dlatencies10
PM_CYC_GRP22 Processor cycles 2 Group 22 pm_dlatencies10
PM_DATA_FROM_L35_MOD_CYC_GRP22 Load latency from L3.5 modified 3 Group 22 pm_dlatencies10
PM_INST_FROM_L2_GRP23 Instructions fetched from L2 0 Group 23 pm_isource
PM_INST_FROM_L21_GRP23 Instruction fetched from private L2 other core 1 Group 23 pm_isource
PM_INST_FROM_L25_MOD_GRP23 Instruction fetched from L2.5 modified 2 Group 23 pm_isource
PM_INST_FROM_L2MISS_GRP23 Instructions fetched missed L2 3 Group 23 pm_isource
PM_INST_FROM_L35_MOD_GRP24 Instruction fetched from L3.5 modified 0 Group 24 pm_isource2
PM_INST_FROM_L35_SHR_GRP24 Instruction fetched from L3.5 shared 1 Group 24 pm_isource2
PM_INST_FROM_L3_GRP24 Instruction fetched from L3 2 Group 24 pm_isource2
PM_INST_FROM_L25_SHR_GRP24 Instruction fetched from L2.5 shared 3 Group 24 pm_isource2
PM_INST_FROM_RL2L3_MOD_GRP25 Instruction fetched from remote L2 or L3 modified 0 Group 25 pm_isource3
PM_INST_FROM_RL2L3_SHR_GRP25 Instruction fetched from remote L2 or L3 shared 1 Group 25 pm_isource3
PM_INST_FROM_DL2L3_SHR_GRP25 Instruction fetched from distant L2 or L3 shared 2 Group 25 pm_isource3
PM_INST_FROM_DL2L3_MOD_GRP25 Instruction fetched from distant L2 or L3 modified 3 Group 25 pm_isource3
PM_INST_FROM_MEM_DP_GRP26 Instruction fetched from double pump memory 0 Group 26 pm_isource4
PM_INST_FROM_DMEM_GRP26 Instruction fetched from distant memory 1 Group 26 pm_isource4
PM_INST_FROM_RMEM_GRP26 Instruction fetched from remote memory 2 Group 26 pm_isource4
PM_INST_FROM_LMEM_GRP26 Instruction fetched from local memory 3 Group 26 pm_isource4
PM_INST_FROM_L2_GRP27 Instructions fetched from L2 0 Group 27 pm_isource5
PM_INST_FROM_L21_GRP27 Instruction fetched from private L2 other core 1 Group 27 pm_isource5
PM_INST_FROM_L3MISS_GRP27 Instruction fetched missed L3 2 Group 27 pm_isource5
PM_INST_FROM_L2MISS_GRP27 Instructions fetched missed L2 3 Group 27 pm_isource5
PM_PTEG_FROM_L2_GRP28 PTEG loaded from L2 0 Group 28 pm_pteg
PM_PTEG_FROM_L21_GRP28 PTEG loaded from private L2 other core 1 Group 28 pm_pteg
PM_PTEG_FROM_L25_MOD_GRP28 PTEG loaded from L2.5 modified 2 Group 28 pm_pteg
PM_PTEG_FROM_L25_SHR_GRP28 PTEG loaded from L2.5 shared 3 Group 28 pm_pteg
PM_PTEG_FROM_L2MISS_GRP29 PTEG loaded from L2 miss 0 Group 29 pm_pteg2
PM_PTEG_FROM_L21_GRP29 PTEG loaded from private L2 other core 1 Group 29 pm_pteg2
PM_PTEG_FROM_L3_GRP29 PTEG loaded from L3 2 Group 29 pm_pteg2
PM_PTEG_FROM_DL2L3_MOD_GRP29 PTEG loaded from distant L2 or L3 modified 3 Group 29 pm_pteg2
PM_PTEG_FROM_L35_MOD_GRP30 PTEG loaded from L3.5 modified 0 Group 30 pm_pteg3
PM_PTEG_FROM_L35_SHR_GRP30 PTEG loaded from L3.5 shared 1 Group 30 pm_pteg3
PM_PTEG_FROM_L3MISS_GRP30 PTEG loaded from L3 miss 2 Group 30 pm_pteg3
PM_PTEG_FROM_LMEM_GRP30 PTEG loaded from local memory 3 Group 30 pm_pteg3
PM_PTEG_FROM_MEM_DP_GRP31 PTEG loaded from double pump memory 0 Group 31 pm_pteg4
PM_PTEG_FROM_DMEM_GRP31 PTEG loaded from distant memory 1 Group 31 pm_pteg4
PM_PTEG_FROM_RMEM_GRP31 PTEG loaded from remote memory 2 Group 31 pm_pteg4
PM_PTEG_FROM_LMEM_GRP31 PTEG loaded from local memory 3 Group 31 pm_pteg4
PM_PTEG_FROM_RL2L3_MOD_GRP32 PTEG loaded from remote L2 or L3 modified 0 Group 32 pm_pteg5
PM_PTEG_FROM_RL2L3_SHR_GRP32 PTEG loaded from remote L2 or L3 shared 1 Group 32 pm_pteg5
PM_PTEG_FROM_DL2L3_SHR_GRP32 PTEG loaded from distant L2 or L3 shared 2 Group 32 pm_pteg5
PM_PTEG_RELOAD_VALID_GRP32 TLB reload valid 3 Group 32 pm_pteg5
PM_DATA_PTEG_1ST_HALF_GRP33 Data table walk matched in first half primary PTEG 0 Group 33 pm_data_tablewalk
PM_DATA_PTEG_2ND_HALF_GRP33 Data table walk matched in second half primary PTEG 1 Group 33 pm_data_tablewalk
PM_DATA_PTEG_SECONDARY_GRP33 Data table walk matched in secondary PTEG 2 Group 33 pm_data_tablewalk
PM_TLB_REF_GRP33 TLB reference 3 Group 33 pm_data_tablewalk
PM_INST_PTEG_1ST_HALF_GRP34 Instruction table walk matched in first half primary PTEG 0 Group 34 pm_inst_tablewalk
PM_INST_PTEG_2ND_HALF_GRP34 Instruction table walk matched in second half primary PTEG 1 Group 34 pm_inst_tablewalk
PM_INST_PTEG_SECONDARY_GRP34 Instruction table walk matched in secondary PTEG 2 Group 34 pm_inst_tablewalk
PM_INST_TABLEWALK_CYC_GRP34 Cycles doing instruction tablewalks 3 Group 34 pm_inst_tablewalk
PM_DPU_HELD_THERMAL_GRP35 DISP unit held due to thermal condition 0 Group 35 pm_freq
PM_DPU_HELD_POWER_GRP35 DISP unit held due to Power Management 1 Group 35 pm_freq
PM_FREQ_DOWN_GRP35 Frequency is being slewed down due to Power Management 2 Group 35 pm_freq
PM_FREQ_UP_GRP35 Frequency is being slewed up due to Power Management 3 Group 35 pm_freq
PM_L1_ICACHE_MISS_GRP36 L1 I cache miss count 0 Group 36 pm_disp_wait
PM_DPU_WT_IC_MISS_GRP36 Cycles DISP unit is stalled due to I cache miss 1 Group 36 pm_disp_wait
PM_DPU_WT_GRP36 Cycles DISP unit is stalled waiting for instructions 2 Group 36 pm_disp_wait
PM_DPU_WT_BR_MPRED_GRP36 Cycles DISP unit is stalled due to branch misprediction 3 Group 36 pm_disp_wait
PM_DPU_HELD_THERMAL_GRP37 DISP unit held due to thermal condition 0 Group 37 pm_disp_held
PM_DPU_HELD_POWER_GRP37 DISP unit held due to Power Management 1 Group 37 pm_disp_held
PM_THERMAL_MAX_GRP37 Processor in thermal MAX 2 Group 37 pm_disp_held
PM_DPU_HELD_SMT_GRP37 DISP unit held due to SMT conflicts 3 Group 37 pm_disp_held
PM_DPU_HELD_GPR_GRP38 DISP unit held due to GPR dependencies 0 Group 38 pm_disp_held2
PM_DPU_HELD_GRP38 DISP unit held 1 Group 38 pm_disp_held2
PM_DPU_HELD_CW_GRP38 DISP unit held due to cache writes 2 Group 38 pm_disp_held2
PM_DPU_HELD_FPQ_GRP38 DISP unit held due to FPU issue queue full 3 Group 38 pm_disp_held2
PM_DPU_HELD_XER_GRP39 DISP unit held due to XER dependency 0 Group 39 pm_disp_held3
PM_DPU_HELD_ISYNC_GRP39 DISP unit held due to ISYNC 1 Group 39 pm_disp_held3
PM_DPU_HELD_STCX_CR_GRP39 DISP unit held due to STCX updating CR 2 Group 39 pm_disp_held3
PM_DPU_HELD_RU_WQ_GRP39 DISP unit held due to RU FXU write queue full 3 Group 39 pm_disp_held3
PM_DPU_HELD_FPU_CR_GRP40 DISP unit held due to FPU updating CR 0 Group 40 pm_disp_held4
PM_DPU_HELD_LSU_GRP40 DISP unit held due to LSU move or invalidate SLB and SR 1 Group 40 pm_disp_held4
PM_DPU_HELD_ITLB_ISLB_GRP40 DISP unit held due to SLB or TLB invalidates 2 Group 40 pm_disp_held4
PM_DPU_HELD_FXU_MULTI_GRP40 DISP unit held due to FXU multicycle 3 Group 40 pm_disp_held4
PM_DPU_HELD_FP_FX_MULT_GRP41 DISP unit held due to non fixed multiple/divide after fixed multiply/divide 0 Group 41 pm_disp_held5
PM_DPU_HELD_MULT_GPR_GRP41 DISP unit held due to multiple/divide multiply/divide GPR dependencies 1 Group 41 pm_disp_held5
PM_DPU_HELD_COMPLETION_GRP41 DISP unit held due to completion holding dispatch 2 Group 41 pm_disp_held5
PM_DPU_HELD_GPR_GRP41 DISP unit held due to GPR dependencies 3 Group 41 pm_disp_held5
PM_DPU_HELD_INT_GRP42 DISP unit held due to exception 0 Group 42 pm_disp_held6
PM_DPU_HELD_XTHRD_GRP42 DISP unit held due to cross thread resource conflicts 1 Group 42 pm_disp_held6
PM_DPU_HELD_LLA_END_GRP42 DISP unit held due to load look ahead ended 2 Group 42 pm_disp_held6
PM_DPU_HELD_RESTART_GRP42 DISP unit held after restart coming 3 Group 42 pm_disp_held6
PM_DPU_HELD_FXU_SOPS_GRP43 DISP unit held due to FXU slow ops (mtmsr, scv, rfscv) 0 Group 43 pm_disp_held7
PM_DPU_HELD_THRD_PRIO_GRP43 DISP unit held due to lower priority thread 1 Group 43 pm_disp_held7
PM_DPU_HELD_SPR_GRP43 DISP unit held due to MTSPR/MFSPR 2 Group 43 pm_disp_held7
PM_DPU_HELD_CR_LOGICAL_GRP43 DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR 3 Group 43 pm_disp_held7
PM_DPU_HELD_ISYNC_GRP44 DISP unit held due to ISYNC 0 Group 44 pm_disp_held8
PM_DPU_HELD_STCX_CR_GRP44 DISP unit held due to STCX updating CR 1 Group 44 pm_disp_held8
PM_DPU_HELD_RU_WQ_GRP44 DISP unit held due to RU FXU write queue full 2 Group 44 pm_disp_held8
PM_DPU_HELD_FPU_CR_GRP44 DISP unit held due to FPU updating CR 3 Group 44 pm_disp_held8
PM_DPU_HELD_ISYNC_GRP45 DISP unit held due to ISYNC 0 Group 45 pm_disp_held9
PM_DPU_HELD_FPU_CR_GRP45 DISP unit held due to FPU updating CR 1 Group 45 pm_disp_held9
PM_DPU_HELD_MULT_GPR_GRP45 DISP unit held due to multiple/divide multiply/divide GPR dependencies 2 Group 45 pm_disp_held9
PM_DPU_HELD_COMPLETION_GRP45 DISP unit held due to completion holding dispatch 3 Group 45 pm_disp_held9
PM_LWSYNC_GRP46 Isync instruction completed 0 Group 46 pm_sync
PM_CYC_GRP46 Processor cycles 1 Group 46 pm_sync
PM_SYNC_CYC_GRP46 Sync duration 2 Group 46 pm_sync
PM_DPU_HELD_LSU_SOPS_GRP46 DISP unit held due to LSU slow ops (sync, tlbie, stcx) 3 Group 46 pm_sync
PM_LD_REF_L1_BOTH_GRP47 Both units L1 D cache load reference 0 Group 47 pm_L1_ref
PM_LD_REF_L1_GRP47 L1 D cache load references 1 Group 47 pm_L1_ref
PM_ST_REF_L1_GRP47 L1 D cache store references 2 Group 47 pm_L1_ref
PM_ST_REF_L1_BOTH_GRP47 Both units L1 D cache store reference 3 Group 47 pm_L1_ref
PM_ST_REF_L1_GRP48 L1 D cache store references 0 Group 48 pm_L1_ldst
PM_LD_REF_L1_GRP48 L1 D cache load references 1 Group 48 pm_L1_ldst
PM_ST_MISS_L1_GRP48 L1 D cache store misses 2 Group 48 pm_L1_ldst
PM_LD_MISS_L1_GRP48 L1 D cache load misses 3 Group 48 pm_L1_ldst
PM_DC_PREF_OUT_OF_STREAMS_GRP49 D cache out of streams 0 Group 49 pm_streams
PM_DC_PREF_STREAM_ALLOC_GRP49 D cache new prefetch stream allocated 1 Group 49 pm_streams
PM_L1_PREF_GRP49 L1 cache data prefetches 2 Group 49 pm_streams
PM_IBUF_FULL_CYC_GRP49 Cycles instruction buffer full 3 Group 49 pm_streams
PM_FLUSH_GRP50 Flushes 0 Group 50 pm_flush
PM_FLUSH_ASYNC_GRP50 Flush caused by asynchronous exception 1 Group 50 pm_flush
PM_FLUSH_FPU_GRP50 Flush caused by FPU exception 2 Group 50 pm_flush
PM_FLUSH_FXU_GRP50 Flush caused by FXU exception 3 Group 50 pm_flush
PM_IC_REQ_GRP51 I cache demand of prefetch request 0 Group 51 pm_prefetch
PM_IC_PREF_REQ_GRP51 Instruction prefetch requests 1 Group 51 pm_prefetch
PM_IC_RELOAD_SHR_GRP51 I cache line reloading to be shared by threads 2 Group 51 pm_prefetch
PM_IC_PREF_WRITE_GRP51 Instruction prefetch written into I cache 3 Group 51 pm_prefetch
PM_STCX_GRP52 STCX executed 0 Group 52 pm_stcx
PM_STCX_CANCEL_GRP52 stcx cancel by core 1 Group 52 pm_stcx
PM_STCX_FAIL_GRP52 STCX failed 2 Group 52 pm_stcx
PM_LARX_GRP52 Larx executed 3 Group 52 pm_stcx
PM_LARX_GRP53 Larx executed 0 Group 53 pm_larx
PM_LARX_L1HIT_GRP53 larx hits in L1 1 Group 53 pm_larx
PM_STCX_GRP53 STCX executed 2 Group 53 pm_larx
PM_STCX_FAIL_GRP53 STCX failed 3 Group 53 pm_larx
PM_THRD_ONE_RUN_CYC_GRP54 One of the threads in run cycles 0 Group 54 pm_thread_cyc
PM_THRD_GRP_CMPL_BOTH_CYC_GRP54 Cycles group completed by both threads 1 Group 54 pm_thread_cyc
PM_THRD_CONC_RUN_INST_GRP54 Concurrent run instructions 2 Group 54 pm_thread_cyc
PM_THRD_BOTH_RUN_CYC_GRP54 Both threads in run cycles 3 Group 54 pm_thread_cyc
PM_1PLUS_PPC_CMPL_GRP55 One or more PPC instruction completed 0 Group 55 pm_misc
PM_HV_CYC_GRP55 Hypervisor Cycles 1 Group 55 pm_misc
PM_THRESH_TIMEO_GRP55 Threshold timeout 2 Group 55 pm_misc
PM_THRD_LLA_BOTH_CYC_GRP55 Both threads in Load Look Ahead 3 Group 55 pm_misc
PM_EE_OFF_EXT_INT_GRP56 Cycles MSR(EE) bit off and external interrupt pending 0 Group 56 pm_misc2
PM_EXT_INT_GRP56 External interrupts 1 Group 56 pm_misc2
PM_TB_BIT_TRANS_GRP56 Time Base bit transition 2 Group 56 pm_misc2
PM_0INST_FETCH_GRP56 No instructions fetched 3 Group 56 pm_misc2
PM_ST_FIN_GRP57 Store instructions finished 0 Group 57 pm_misc3
PM_THRD_L2MISS_GRP57 Thread in L2 miss 1 Group 57 pm_misc3
PM_CYC_GRP57 Processor cycles 2 Group 57 pm_misc3
PM_INST_CMPL_GRP57 Instructions completed 3 Group 57 pm_misc3
PM_ISLB_MISS_GRP58 Instruction SLB misses 0 Group 58 pm_tlb_slb
PM_DSLB_MISS_GRP58 Data SLB misses 1 Group 58 pm_tlb_slb
PM_TLB_REF_GRP58 TLB reference 2 Group 58 pm_tlb_slb
PM_ITLB_REF_GRP58 Instruction TLB reference 3 Group 58 pm_tlb_slb
PM_ISLB_MISS_GRP59 Instruction SLB misses 0 Group 59 pm_slb_miss
PM_DSLB_MISS_GRP59 Data SLB misses 1 Group 59 pm_slb_miss
PM_IERAT_MISS_GRP59 IERAT miss count 2 Group 59 pm_slb_miss
PM_SLB_MISS_GRP59 SLB misses 3 Group 59 pm_slb_miss
PM_LSU_REJECT_L2_CORR_GRP60 LSU reject due to L2 correctable error 0 Group 60 pm_rejects
PM_LSU_REJECT_DERAT_MPRED_GRP60 LSU reject due to mispredicted DERAT 1 Group 60 pm_rejects
PM_LSU_REJECT_FAST_GRP60 LSU fast reject 2 Group 60 pm_rejects
PM_LSU_REJECT_GRP60 LSU reject 3 Group 60 pm_rejects
PM_LSU_REJECT_LHS_GRP61 Load hit store reject 0 Group 61 pm_rejects2
PM_LSU_REJECT_LHS_BOTH_GRP61 Load hit store reject both units 1 Group 61 pm_rejects2
PM_LSU_REJECT_EXTERN_GRP61 LSU external reject request 2 Group 61 pm_rejects2
PM_LSU_REJECT_STEAL_GRP61 LSU reject due to steal 3 Group 61 pm_rejects2
PM_LSU_REJECT_STQ_FULL_GRP62 LSU reject due to store queue full 0 Group 62 pm_rejects3
PM_LSU_REJECT_SLOW_GRP62 LSU slow reject 1 Group 62 pm_rejects3
PM_LSU_REJECT_NO_SCRATCH_GRP62 LSU reject due to scratch register not available 2 Group 62 pm_rejects3
PM_LSU_REJECT_PARTIAL_SECTOR_GRP62 LSU reject due to partial sector valid 3 Group 62 pm_rejects3
PM_LSU_REJECT_UST_BOTH_GRP63 Unaligned store reject both units 0 Group 63 pm_rejects4
PM_LSU_REJECT_UST_GRP63 Unaligned store reject 1 Group 63 pm_rejects4
PM_LSU0_REJECT_UST_GRP63 LSU0 unaligned store reject 2 Group 63 pm_rejects4
PM_LSU1_REJECT_UST_GRP63 LSU1 unaligned store reject 3 Group 63 pm_rejects4
PM_LSU_REJECT_ULD_GRP64 Unaligned load reject 0 Group 64 pm_rejects5
PM_LSU_REJECT_ULD_BOTH_GRP64 Unaligned load reject both units 1 Group 64 pm_rejects5
PM_LSU0_REJECT_ULD_GRP64 LSU0 unaligned load reject 2 Group 64 pm_rejects5
PM_LSU1_REJECT_ULD_GRP64 LSU1 unaligned load reject 3 Group 64 pm_rejects5
PM_LSU0_REJECT_SET_MPRED_GRP65 LSU0 reject due to mispredicted set 0 Group 65 pm_rejects6
PM_LSU1_REJECT_SET_MPRED_GRP65 LSU1 reject due to mispredicted set 1 Group 65 pm_rejects6
PM_LSU_REJECT_SET_MPRED_GRP65 LSU reject due to mispredicted set 2 Group 65 pm_rejects6
PM_LSU_SRQ_EMPTY_CYC_GRP65 Cycles SRQ empty 3 Group 65 pm_rejects6
PM_LSU0_REJECT_ULD_GRP66 LSU0 unaligned load reject 0 Group 66 pm_rejects_unit
PM_LSU1_REJECT_UST_GRP66 LSU1 unaligned store reject 1 Group 66 pm_rejects_unit
PM_LSU0_REJECT_UST_GRP66 LSU0 unaligned store reject 2 Group 66 pm_rejects_unit
PM_LSU1_REJECT_ULD_GRP66 LSU1 unaligned load reject 3 Group 66 pm_rejects_unit
PM_LSU0_REJECT_GRP67 LSU0 reject 0 Group 67 pm_rejects_unit2
PM_LSU0_REJECT_DERAT_MPRED_GRP67 LSU0 reject due to mispredicted DERAT 1 Group 67 pm_rejects_unit2
PM_LSU1_REJECT_GRP67 LSU1 reject 2 Group 67 pm_rejects_unit2
PM_LSU1_REJECT_NO_SCRATCH_GRP67 LSU1 reject due to scratch register not available 3 Group 67 pm_rejects_unit2
PM_LSU0_REJECT_EXTERN_GRP68 LSU0 external reject request 0 Group 68 pm_rejects_unit3
PM_LSU0_REJECT_L2_CORR_GRP68 LSU0 reject due to L2 correctable error 1 Group 68 pm_rejects_unit3
PM_LSU1_REJECT_EXTERN_GRP68 LSU1 external reject request 2 Group 68 pm_rejects_unit3
PM_LSU1_REJECT_L2_CORR_GRP68 LSU1 reject due to L2 correctable error 3 Group 68 pm_rejects_unit3
PM_LSU0_REJECT_NO_SCRATCH_GRP69 LSU0 reject due to scratch register not available 0 Group 69 pm_rejects_unit4
PM_LSU0_REJECT_PARTIAL_SECTOR_GRP69 LSU0 reject due to partial sector valid 1 Group 69 pm_rejects_unit4
PM_LSU1_REJECT_NO_SCRATCH_GRP69 LSU1 reject due to scratch register not available 2 Group 69 pm_rejects_unit4
PM_LSU1_REJECT_PARTIAL_SECTOR_GRP69 LSU1 reject due to partial sector valid 3 Group 69 pm_rejects_unit4
PM_LSU0_REJECT_LHS_GRP70 LSU0 load hit store reject 0 Group 70 pm_rejects_unit5
PM_LSU0_DERAT_MISS_GRP70 LSU0 DERAT misses 1 Group 70 pm_rejects_unit5
PM_LSU1_REJECT_LHS_GRP70 LSU1 load hit store reject 2 Group 70 pm_rejects_unit5
PM_LSU1_DERAT_MISS_GRP70 LSU1 DERAT misses 3 Group 70 pm_rejects_unit5
PM_LSU0_REJECT_STQ_FULL_GRP71 LSU0 reject due to store queue full 0 Group 71 pm_rejects_unit6
PM_LSU0_REJECT_GRP71 LSU0 reject 1 Group 71 pm_rejects_unit6
PM_LSU1_REJECT_STQ_FULL_GRP71 LSU1 reject due to store queue full 2 Group 71 pm_rejects_unit6
PM_LSU1_REJECT_GRP71 LSU1 reject 3 Group 71 pm_rejects_unit6
PM_LSU0_REJECT_DERAT_MPRED_GRP72 LSU0 reject due to mispredicted DERAT 0 Group 72 pm_rejects_unit7
PM_LSU0_DERAT_MISS_GRP72 LSU0 DERAT misses 1 Group 72 pm_rejects_unit7
PM_LSU1_REJECT_DERAT_MPRED_GRP72 LSU1 reject due to mispredicted DERAT 2 Group 72 pm_rejects_unit7
PM_LSU1_DERAT_MISS_GRP72 LSU1 DERAT misses 3 Group 72 pm_rejects_unit7
PM_LSU_LDF_BOTH_GRP73 Both LSU units executed Floating Point load instruction 0 Group 73 pm_ldf
PM_LSU_LDF_GRP73 LSU executed Floating Point load instruction 1 Group 73 pm_ldf
PM_LSU0_LDF_GRP73 LSU0 executed Floating Point load instruction 2 Group 73 pm_ldf
PM_LSU1_LDF_GRP73 LSU1 executed Floating Point load instruction 3 Group 73 pm_ldf
PM_LSU0_NCLD_GRP74 LSU0 non-cacheable loads 0 Group 74 pm_lsu_misc
PM_LSU0_NCST_GRP74 LSU0 non-cachable stores 1 Group 74 pm_lsu_misc
PM_LSU_ST_CHAINED_GRP74 number of chained stores 2 Group 74 pm_lsu_misc
PM_LSU_BOTH_BUS_GRP74 Both data return buses busy simultaneously 3 Group 74 pm_lsu_misc
PM_LSU_LMQ_FULL_CYC_GRP75 Cycles LMQ full 0 Group 75 pm_lsu_lmq
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP75 Cycles LMQ and SRQ empty 1 Group 75 pm_lsu_lmq
PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC_GRP75 Cycles both threads LMQ and SRQ empty 2 Group 75 pm_lsu_lmq
PM_LSU0_REJECT_L2MISS_GRP75 LSU0 L2 miss reject 3 Group 75 pm_lsu_lmq
PM_LSU_DERAT_MISS_CYC_GRP76 DERAT miss latency 0 Group 76 pm_lsu_flush_derat_miss
PM_LSU_DERAT_MISS_GRP76 DERAT misses 1 Group 76 pm_lsu_flush_derat_miss
PM_LSU_FLUSH_ALIGN_GRP76 Flush caused by alignement exception 2 Group 76 pm_lsu_flush_derat_miss
PM_LSU_FLUSH_DSI_GRP76 Flush caused by DSI 3 Group 76 pm_lsu_flush_derat_miss
PM_INST_DISP_LLA_GRP77 Instruction dispatched under load look ahead 0 Group 77 pm_lla
PM_DPU_HELD_LLA_END_GRP77 DISP unit held due to load look ahead ended 1 Group 77 pm_lla
PM_INST_DISP_GRP77 Instructions dispatched 2 Group 77 pm_lla
PM_THRD_LLA_BOTH_CYC_GRP77 Both threads in Load Look Ahead 3 Group 77 pm_lla
PM_GCT_NOSLOT_CYC_GRP78 Cycles no GCT slot allocated 0 Group 78 pm_gct
PM_GCT_EMPTY_CYC_GRP78 Cycles GCT empty 1 Group 78 pm_gct
PM_GCT_FULL_CYC_GRP78 Cycles GCT full 2 Group 78 pm_gct
PM_INST_FETCH_CYC_GRP78 Cycles at least 1 instruction fetched 3 Group 78 pm_gct
PM_THRD_PRIO_0_CYC_GRP79 Cycles thread running at priority level 0 0 Group 79 pm_smt_priorities
PM_THRD_PRIO_1_CYC_GRP79 Cycles thread running at priority level 1 1 Group 79 pm_smt_priorities
PM_THRD_PRIO_2_CYC_GRP79 Cycles thread running at priority level 2 2 Group 79 pm_smt_priorities
PM_THRD_PRIO_3_CYC_GRP79 Cycles thread running at priority level 3 3 Group 79 pm_smt_priorities
PM_THRD_PRIO_7_CYC_GRP80 Cycles thread running at priority level 7 0 Group 80 pm_smt_priorities2
PM_THRD_PRIO_6_CYC_GRP80 Cycles thread running at priority level 6 1 Group 80 pm_smt_priorities2
PM_THRD_PRIO_5_CYC_GRP80 Cycles thread running at priority level 5 2 Group 80 pm_smt_priorities2
PM_THRD_PRIO_4_CYC_GRP80 Cycles thread running at priority level 4 3 Group 80 pm_smt_priorities2
PM_THRD_PRIO_DIFF_0_CYC_GRP81 Cycles no thread priority difference 0 Group 81 pm_smt_priorities3
PM_THRD_PRIO_DIFF_1or2_CYC_GRP81 Cycles thread priority difference is 1 or 2 1 Group 81 pm_smt_priorities3
PM_THRD_PRIO_DIFF_3or4_CYC_GRP81 Cycles thread priority difference is 3 or 4 2 Group 81 pm_smt_priorities3
PM_THRD_PRIO_DIFF_5or6_CYC_GRP81 Cycles thread priority difference is 5 or 6 3 Group 81 pm_smt_priorities3
PM_THRD_SEL_T0_GRP82 Decode selected thread 0 0 Group 82 pm_smt_priorities4
PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP82 Cycles thread priority difference is -1 or -2 1 Group 82 pm_smt_priorities4
PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP82 Cycles thread priority difference is -3 or -4 2 Group 82 pm_smt_priorities4
PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP82 Cycles thread priority difference is -5 or -6 3 Group 82 pm_smt_priorities4
PM_FXU_IDLE_GRP83 FXU idle 0 Group 83 pm_fxu
PM_FXU_BUSY_GRP83 FXU busy 1 Group 83 pm_fxu
PM_FXU0_BUSY_FXU1_IDLE_GRP83 FXU0 busy FXU1 idle 2 Group 83 pm_fxu
PM_FXU1_BUSY_FXU0_IDLE_GRP83 FXU1 busy FXU0 idle 3 Group 83 pm_fxu
PM_FXU_PIPELINED_MULT_DIV_GRP84 Fix point multiply/divide pipelined 0 Group 84 pm_fxu2
PM_IFU_FIN_GRP84 IFU finished an instruction 1 Group 84 pm_fxu2
PM_FXU0_FIN_GRP84 FXU0 produced a result 2 Group 84 pm_fxu2
PM_FXU1_FIN_GRP84 FXU1 produced a result 3 Group 84 pm_fxu2
PM_VMX_COMPLEX_ISUED_GRP85 VMX instruction issued to complex 0 Group 85 pm_vmx
PM_VMX_FLOAT_ISSUED_GRP85 VMX instruction issued to float 1 Group 85 pm_vmx
PM_VMX_SIMPLE_ISSUED_GRP85 VMX instruction issued to simple 2 Group 85 pm_vmx
PM_VMX_PERMUTE_ISSUED_GRP85 VMX instruction issued to permute 3 Group 85 pm_vmx
PM_VMX0_INST_ISSUED_GRP86 VMX0 instruction issued 0 Group 86 pm_vmx2
PM_VMX1_INST_ISSUED_GRP86 VMX1 instruction issued 1 Group 86 pm_vmx2
PM_VMX0_LD_ISSUED_GRP86 VMX0 load issued 2 Group 86 pm_vmx2
PM_VMX1_LD_ISSUED_GRP86 VMX1 load issued 3 Group 86 pm_vmx2
PM_VMX0_LD_ISSUED_GRP87 VMX0 load issued 0 Group 87 pm_vmx3
PM_VMX0_LD_WRBACK_GRP87 VMX0 load writeback valid 1 Group 87 pm_vmx3
PM_VMX1_LD_ISSUED_GRP87 VMX1 load issued 2 Group 87 pm_vmx3
PM_VMX1_LD_WRBACK_GRP87 VMX1 load writeback valid 3 Group 87 pm_vmx3
PM_VMX_FLOAT_MULTICYCLE_GRP88 VMX multi-cycle floating point instruction issued 0 Group 88 pm_vmx4
PM_VMX_RESULT_SAT_0_1_GRP88 VMX valid result with sat bit is set (0->1) 1 Group 88 pm_vmx4
PM_VMX_RESULT_SAT_1_GRP88 VMX valid result with sat=1 2 Group 88 pm_vmx4
PM_VMX_ST_ISSUED_GRP88 VMX store issued 3 Group 88 pm_vmx4
PM_VMX_ST_ISSUED_GRP89 VMX store issued 0 Group 89 pm_vmx5
PM_VMX0_STALL_GRP89 VMX0 stall 1 Group 89 pm_vmx5
PM_VMX1_STALL_GRP89 VMX1 stall 2 Group 89 pm_vmx5
PM_VMX_FLOAT_MULTICYCLE_GRP89 VMX multi-cycle floating point instruction issued 3 Group 89 pm_vmx5
PM_DFU_ADD_GRP90 DFU add type instruction 0 Group 90 pm_dfu
PM_DFU_ADD_SHIFTED_BOTH_GRP90 DFU add type with both operands shifted 1 Group 90 pm_dfu
PM_DFU_BACK2BACK_GRP90 DFU back to back operations executed 2 Group 90 pm_dfu
PM_DFU_CONV_GRP90 DFU convert from fixed op 3 Group 90 pm_dfu
PM_DFU_ENC_BCD_DPD_GRP91 DFU Encode BCD to DPD 0 Group 91 pm_dfu2
PM_DFU_EXP_EQ_GRP91 DFU operand exponents are equal for add type 1 Group 91 pm_dfu2
PM_DFU_FIN_GRP91 DFU instruction finish 2 Group 91 pm_dfu2
PM_DFU_SUBNORM_GRP91 DFU result is a subnormal 3 Group 91 pm_dfu2
PM_FAB_CMD_ISSUED_GRP92 Fabric command issued 0 Group 92 pm_fab
PM_FAB_CMD_RETRIED_GRP92 Fabric command retried 1 Group 92 pm_fab
PM_FAB_DCLAIM_GRP92 Dclaim operation, locally mastered 2 Group 92 pm_fab
PM_FAB_DMA_GRP92 DMA operation, locally mastered 3 Group 92 pm_fab
PM_FAB_NODE_PUMP_GRP93 Node pump operation, locally mastered 0 Group 93 pm_fab2
PM_FAB_RETRY_NODE_PUMP_GRP93 Retry of a node pump, locally mastered 1 Group 93 pm_fab2
PM_FAB_RETRY_SYS_PUMP_GRP93 Retry of a system pump, locally mastered 2 Group 93 pm_fab2
PM_FAB_SYS_PUMP_GRP93 System pump operation, locally mastered 3 Group 93 pm_fab2
PM_FAB_CMD_ISSUED_GRP94 Fabric command issued 0 Group 94 pm_fab3
PM_FAB_CMD_RETRIED_GRP94 Fabric command retried 1 Group 94 pm_fab3
PM_FAB_ADDR_COLLISION_GRP94 local node launch collision with off-node address 2 Group 94 pm_fab3
PM_FAB_MMIO_GRP94 MMIO operation, locally mastered 3 Group 94 pm_fab3
PM_MEM_DP_RQ_GLOB_LOC_GRP95 Memory read queue marking cache line double pump state from global to local 0 Group 95 pm_mem_dblpump
PM_MEM_DP_RQ_LOC_GLOB_GRP95 Memory read queue marking cache line double pump state from local to global 1 Group 95 pm_mem_dblpump
PM_MEM_DP_CL_WR_GLOB_GRP95 cache line write setting double pump state to global 2 Group 95 pm_mem_dblpump
PM_MEM_DP_CL_WR_LOC_GRP95 cache line write setting double pump state to local 3 Group 95 pm_mem_dblpump
PM_MEM0_DP_RQ_GLOB_LOC_GRP96 Memory read queue marking cache line double pump state from global to local side 0 0 Group 96 pm_mem0_dblpump
PM_MEM0_DP_RQ_LOC_GLOB_GRP96 Memory read queue marking cache line double pump state from local to global side 0 1 Group 96 pm_mem0_dblpump
PM_MEM0_DP_CL_WR_GLOB_GRP96 cacheline write setting dp to global side 0 2 Group 96 pm_mem0_dblpump
PM_MEM0_DP_CL_WR_LOC_GRP96 cacheline write setting dp to local side 0 3 Group 96 pm_mem0_dblpump
PM_MEM1_DP_RQ_GLOB_LOC_GRP97 Memory read queue marking cache line double pump state from global to local side 1 0 Group 97 pm_mem1_dblpump
PM_MEM1_DP_RQ_LOC_GLOB_GRP97 Memory read queue marking cache line double pump state from local to global side 1 1 Group 97 pm_mem1_dblpump
PM_MEM1_DP_CL_WR_GLOB_GRP97 cacheline write setting dp to global side 1 2 Group 97 pm_mem1_dblpump
PM_MEM1_DP_CL_WR_LOC_GRP97 cacheline write setting dp to local side 1 3 Group 97 pm_mem1_dblpump
PM_GXO_CYC_BUSY_GRP98 Outbound GX bus utilizations (# of cycles in use) 0 Group 98 pm_gxo
PM_GXO_ADDR_CYC_BUSY_GRP98 Outbound GX address utilization (# of cycles address out is valid) 1 Group 98 pm_gxo
PM_GXO_DATA_CYC_BUSY_GRP98 Outbound GX Data utilization (# of cycles data out is valid) 2 Group 98 pm_gxo
PM_GXI_CYC_BUSY_GRP98 Inbound GX bus utilizations (# of cycles in use) 3 Group 98 pm_gxo
PM_GXI_CYC_BUSY_GRP99 Inbound GX bus utilizations (# of cycles in use) 0 Group 99 pm_gxi
PM_GXI_ADDR_CYC_BUSY_GRP99 Inbound GX address utilization (# of cycle address is in valid) 1 Group 99 pm_gxi
PM_GXI_DATA_CYC_BUSY_GRP99 Inbound GX Data utilization (# of cycle data in is valid) 2 Group 99 pm_gxi
PM_GXO_CYC_BUSY_GRP99 Outbound GX bus utilizations (# of cycles in use) 3 Group 99 pm_gxi
PM_GXO_CYC_BUSY_GRP100 Outbound GX bus utilizations (# of cycles in use) 0 Group 100 pm_gx_dma
PM_GXI_CYC_BUSY_GRP100 Inbound GX bus utilizations (# of cycles in use) 1 Group 100 pm_gx_dma
PM_GX_DMA_READ_GRP100 DMA Read Request 2 Group 100 pm_gx_dma
PM_GX_DMA_WRITE_GRP100 All DMA Write Requests (including dma wrt lgcy) 3 Group 100 pm_gx_dma
PM_INST_FROM_L1_GRP101 Instruction fetched from L1 0 Group 101 pm_L1_misc
PM_L1_WRITE_CYC_GRP101 Cycles writing to instruction L1 1 Group 101 pm_L1_misc
PM_NO_ITAG_CYC_GRP101 Cyles no ITAG available 2 Group 101 pm_L1_misc
PM_INST_IMC_MATCH_CMPL_GRP101 IMC matched instructions completed 3 Group 101 pm_L1_misc
PM_L2_LD_REQ_DATA_GRP102 L2 data load requests 0 Group 102 pm_L2_data
PM_L2_LD_MISS_DATA_GRP102 L2 data load misses 1 Group 102 pm_L2_data
PM_L2_ST_REQ_DATA_GRP102 L2 data store requests 2 Group 102 pm_L2_data
PM_L2_ST_MISS_DATA_GRP102 L2 data store misses 3 Group 102 pm_L2_data
PM_L2_LD_REQ_INST_GRP103 L2 instruction load requests 0 Group 103 pm_L2_ld_inst
PM_L2_LD_MISS_INST_GRP103 L2 instruction load misses 1 Group 103 pm_L2_ld_inst
PM_L2_MISS_GRP103 L2 cache misses 2 Group 103 pm_L2_ld_inst
PM_L2_PREF_LD_GRP103 L2 cache prefetches 3 Group 103 pm_L2_ld_inst
PM_L2_CASTOUT_MOD_GRP104 L2 castouts - Modified (M, Mu, Me) 0 Group 104 pm_L2_castout_invalidate
PM_L2_CASTOUT_SHR_GRP104 L2 castouts - Shared (T, Te, Si, S) 1 Group 104 pm_L2_castout_invalidate
PM_IC_INV_L2_GRP104 L1 I cache entries invalidated from L2 2 Group 104 pm_L2_castout_invalidate
PM_DC_INV_L2_GRP104 L1 D cache entries invalidated from L2 3 Group 104 pm_L2_castout_invalidate
PM_LD_REQ_L2_GRP105 L2 load requests 0 Group 105 pm_L2_ldst_reqhit
PM_LD_HIT_L2_GRP105 L2 D cache load hits 1 Group 105 pm_L2_ldst_reqhit
PM_ST_REQ_L2_GRP105 L2 store requests 2 Group 105 pm_L2_ldst_reqhit
PM_ST_HIT_L2_GRP105 L2 D cache store hits 3 Group 105 pm_L2_ldst_reqhit
PM_L2SA_LD_REQ_DATA_GRP106 L2 slice A data load requests 0 Group 106 pm_L2_ld_data_slice
PM_L2SA_LD_MISS_DATA_GRP106 L2 slice A data load misses 1 Group 106 pm_L2_ld_data_slice
PM_L2SB_LD_REQ_DATA_GRP106 L2 slice B data load requests 2 Group 106 pm_L2_ld_data_slice
PM_L2SB_LD_MISS_DATA_GRP106 L2 slice B data load misses 3 Group 106 pm_L2_ld_data_slice
PM_L2SA_LD_REQ_INST_GRP107 L2 slice A instruction load requests 0 Group 107 pm_L2_ld_inst_slice
PM_L2SA_LD_MISS_INST_GRP107 L2 slice A instruction load misses 1 Group 107 pm_L2_ld_inst_slice
PM_L2SB_LD_REQ_INST_GRP107 L2 slice B instruction load requests 2 Group 107 pm_L2_ld_inst_slice
PM_L2SB_LD_MISS_INST_GRP107 L2 slice B instruction load misses 3 Group 107 pm_L2_ld_inst_slice
PM_L2SA_ST_REQ_GRP108 L2 slice A store requests 0 Group 108 pm_L2_st_slice
PM_L2SA_ST_MISS_GRP108 L2 slice A store misses 1 Group 108 pm_L2_st_slice
PM_L2SB_ST_REQ_GRP108 L2 slice B store requests 2 Group 108 pm_L2_st_slice
PM_L2SB_ST_MISS_GRP108 L2 slice B store misses 3 Group 108 pm_L2_st_slice
PM_L2SA_MISS_GRP109 L2 slice A misses 0 Group 109 pm_L2miss_slice
PM_L2_MISS_GRP109 L2 cache misses 1 Group 109 pm_L2miss_slice
PM_DATA_FROM_L2MISS_GRP109 Data loaded missed L2 2 Group 109 pm_L2miss_slice
PM_L2SB_MISS_GRP109 L2 slice B misses 3 Group 109 pm_L2miss_slice
PM_L2SA_CASTOUT_MOD_GRP110 L2 slice A castouts - Modified 0 Group 110 pm_L2_castout_slice
PM_L2SA_CASTOUT_SHR_GRP110 L2 slice A castouts - Shared 1 Group 110 pm_L2_castout_slice
PM_L2SB_CASTOUT_MOD_GRP110 L2 slice B castouts - Modified 2 Group 110 pm_L2_castout_slice
PM_L2SB_CASTOUT_SHR_GRP110 L2 slice B castouts - Shared 3 Group 110 pm_L2_castout_slice
PM_L2SA_IC_INV_GRP111 L2 slice A I cache invalidate 0 Group 111 pm_L2_invalidate_slice
PM_L2SA_DC_INV_GRP111 L2 slice A D cache invalidate 1 Group 111 pm_L2_invalidate_slice
PM_L2SB_IC_INV_GRP111 L2 slice B I cache invalidate 2 Group 111 pm_L2_invalidate_slice
PM_L2SB_DC_INV_GRP111 L2 slice B D cache invalidate 3 Group 111 pm_L2_invalidate_slice
PM_L2SA_LD_REQ_GRP112 L2 slice A load requests 0 Group 112 pm_L2_ld_reqhit_slice
PM_L2SA_LD_HIT_GRP112 L2 slice A load hits 1 Group 112 pm_L2_ld_reqhit_slice
PM_L2SB_LD_REQ_GRP112 L2 slice B load requests 2 Group 112 pm_L2_ld_reqhit_slice
PM_L2SB_LD_HIT_GRP112 L2 slice B load hits 3 Group 112 pm_L2_ld_reqhit_slice
PM_L2SA_ST_REQ_GRP113 L2 slice A store requests 0 Group 113 pm_L2_st_reqhit_slice
PM_L2SA_ST_HIT_GRP113 L2 slice A store hits 1 Group 113 pm_L2_st_reqhit_slice
PM_L2SB_ST_REQ_GRP113 L2 slice B store requests 2 Group 113 pm_L2_st_reqhit_slice
PM_L2SB_ST_HIT_GRP113 L2 slice B store hits 3 Group 113 pm_L2_st_reqhit_slice
PM_IC_DEMAND_L2_BHT_REDIRECT_GRP114 L2 I cache demand request due to BHT redirect 0 Group 114 pm_L2_redir_pref
PM_IC_DEMAND_L2_BR_REDIRECT_GRP114 L2 I cache demand request due to branch redirect 1 Group 114 pm_L2_redir_pref
PM_L2_PREF_ST_GRP114 L2 cache prefetches 2 Group 114 pm_L2_redir_pref
PM_L2_PREF_LD_GRP114 L2 cache prefetches 3 Group 114 pm_L2_redir_pref
PM_L3SA_REF_GRP115 L3 slice A references 0 Group 115 pm_L3_SliceA
PM_L3SA_HIT_GRP115 L3 slice A hits 1 Group 115 pm_L3_SliceA
PM_DATA_FROM_L3_GRP115 Data loaded from L3 2 Group 115 pm_L3_SliceA
PM_L3SA_MISS_GRP115 L3 slice A misses 3 Group 115 pm_L3_SliceA
PM_L3SB_REF_GRP116 L3 slice B references 0 Group 116 pm_L3_SliceB
PM_L3SB_HIT_GRP116 L3 slice B hits 1 Group 116 pm_L3_SliceB
PM_DATA_FROM_L3_GRP116 Data loaded from L3 2 Group 116 pm_L3_SliceB
PM_L3SB_MISS_GRP116 L3 slice B misses 3 Group 116 pm_L3_SliceB
PM_FPU_ISSUE_0_GRP117 FPU issue 0 per cycle 0 Group 117 pm_fpu_issue
PM_FPU_ISSUE_1_GRP117 FPU issue 1 per cycle 1 Group 117 pm_fpu_issue
PM_FPU_ISSUE_2_GRP117 FPU issue 2 per cycle 2 Group 117 pm_fpu_issue
PM_FPU_ISSUE_STEERING_GRP117 FPU issue steering 3 Group 117 pm_fpu_issue
PM_FPU_ISSUE_OOO_GRP118 FPU issue out-of-order 0 Group 118 pm_fpu_issue2
PM_FPU_ISSUE_ST_FOLDED_GRP118 FPU issue a folded store 1 Group 118 pm_fpu_issue2
PM_FPU_ISSUE_DIV_SQRT_OVERLAP_GRP118 FPU divide/sqrt overlapped with other divide/sqrt 2 Group 118 pm_fpu_issue2
PM_FPU_ISSUE_STALL_ST_GRP118 FPU issue stalled due to store 3 Group 118 pm_fpu_issue2
PM_FPU_ISSUE_STALL_THRD_GRP119 FPU issue stalled due to thread resource conflict 0 Group 119 pm_fpu_issue3
PM_FPU_ISSUE_STALL_FPR_GRP119 FPU issue stalled due to FPR dependencies 1 Group 119 pm_fpu_issue3
PM_FPU_ISSUE_DIV_SQRT_OVERLAP_GRP119 FPU divide/sqrt overlapped with other divide/sqrt 2 Group 119 pm_fpu_issue3
PM_FPU_ISSUE_STALL_ST_GRP119 FPU issue stalled due to store 3 Group 119 pm_fpu_issue3
PM_FPU0_1FLOP_GRP120 FPU0 executed add, mult, sub, cmp or sel instruction 0 Group 120 pm_fpu0_flop
PM_FPU0_FMA_GRP120 FPU0 executed multiply-add instruction 1 Group 120 pm_fpu0_flop
PM_FPU0_FSQRT_FDIV_GRP120 FPU0 executed FSQRT or FDIV instruction 2 Group 120 pm_fpu0_flop
PM_FPU0_STF_GRP120 FPU0 executed store instruction 3 Group 120 pm_fpu0_flop
PM_FPU0_FLOP_GRP121 FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction 0 Group 121 pm_fpu0_misc
PM_FPU0_FXDIV_GRP121 FPU0 executed fixed point division 1 Group 121 pm_fpu0_misc
PM_FPU0_DENORM_GRP121 FPU0 received denormalized data 2 Group 121 pm_fpu0_misc
PM_FPU0_SINGLE_GRP121 FPU0 executed single precision instruction 3 Group 121 pm_fpu0_misc
PM_FPU0_FIN_GRP122 FPU0 produced a result 0 Group 122 pm_fpu0_misc2
PM_FPU0_FEST_GRP122 FPU0 executed FEST instruction 1 Group 122 pm_fpu0_misc2
PM_FPU0_FPSCR_GRP122 FPU0 executed FPSCR instruction 2 Group 122 pm_fpu0_misc2
PM_FPU0_FXMULT_GRP122 FPU0 executed fixed point multiplication 3 Group 122 pm_fpu0_misc2
PM_FPU0_FCONV_GRP123 FPU0 executed FCONV instruction 0 Group 123 pm_fpu0_misc3
PM_FPU0_FRSP_GRP123 FPU0 executed FRSP instruction 1 Group 123 pm_fpu0_misc3
PM_FPU0_ST_FOLDED_GRP123 FPU0 folded store 2 Group 123 pm_fpu0_misc3
PM_FPU0_FEST_GRP123 FPU0 executed FEST instruction 3 Group 123 pm_fpu0_misc3
PM_FPU1_1FLOP_GRP124 FPU1 executed add, mult, sub, cmp or sel instruction 0 Group 124 pm_fpu1_flop
PM_FPU1_FMA_GRP124 FPU1 executed multiply-add instruction 1 Group 124 pm_fpu1_flop
PM_FPU1_FSQRT_FDIV_GRP124 FPU1 executed FSQRT or FDIV instruction 2 Group 124 pm_fpu1_flop
PM_FPU1_STF_GRP124 FPU1 executed store instruction 3 Group 124 pm_fpu1_flop
PM_FPU1_FLOP_GRP125 FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction 0 Group 125 pm_fpu1_misc
PM_FPU1_FXDIV_GRP125 FPU1 executed fixed point division 1 Group 125 pm_fpu1_misc
PM_FPU1_DENORM_GRP125 FPU1 received denormalized data 2 Group 125 pm_fpu1_misc
PM_FPU1_SINGLE_GRP125 FPU1 executed single precision instruction 3 Group 125 pm_fpu1_misc
PM_FPU1_FIN_GRP126 FPU1 produced a result 0 Group 126 pm_fpu1_misc2
PM_FPU1_FEST_GRP126 FPU1 executed FEST instruction 1 Group 126 pm_fpu1_misc2
PM_FPU1_FPSCR_GRP126 FPU1 executed FPSCR instruction 2 Group 126 pm_fpu1_misc2
PM_FPU1_FXMULT_GRP126 FPU1 executed fixed point multiplication 3 Group 126 pm_fpu1_misc2
PM_FPU1_FCONV_GRP127 FPU1 executed FCONV instruction 0 Group 127 pm_fpu1_misc3
PM_FPU1_FRSP_GRP127 FPU1 executed FRSP instruction 1 Group 127 pm_fpu1_misc3
PM_FPU1_ST_FOLDED_GRP127 FPU1 folded store 2 Group 127 pm_fpu1_misc3
PM_FPU1_FEST_GRP127 FPU1 executed FEST instruction 3 Group 127 pm_fpu1_misc3
PM_FPU_1FLOP_GRP128 FPU executed one flop instruction 0 Group 128 pm_fpu_flop
PM_FPU_FMA_GRP128 FPU executed multiply-add instruction 1 Group 128 pm_fpu_flop
PM_FPU_FSQRT_FDIV_GRP128 FPU executed FSQRT or FDIV instruction 2 Group 128 pm_fpu_flop
PM_FPU_FLOP_GRP128 FPU executed 1FLOP, FMA, FSQRT or FDIV instruction 3 Group 128 pm_fpu_flop
PM_FPU_FIN_GRP129 FPU produced a result 0 Group 129 pm_fpu_misc
PM_FPU_FRSP_GRP129 FPU executed FRSP instruction 1 Group 129 pm_fpu_misc
PM_FPU_FPSCR_GRP129 FPU executed FPSCR instruction 2 Group 129 pm_fpu_misc
PM_FPU_FXMULT_GRP129 FPU executed fixed point multiplication 3 Group 129 pm_fpu_misc
PM_FPU_FXDIV_GRP130 FPU executed fixed point division 0 Group 130 pm_fpu_misc2
PM_FPU_DENORM_GRP130 FPU received denormalized data 1 Group 130 pm_fpu_misc2
PM_FPU_STF_GRP130 FPU executed store instruction 2 Group 130 pm_fpu_misc2
PM_FPU_SINGLE_GRP130 FPU executed single precision instruction 3 Group 130 pm_fpu_misc2
PM_FPU_FCONV_GRP131 FPU executed FCONV instruction 0 Group 131 pm_fpu_misc3
PM_FPU_FRSP_GRP131 FPU executed FRSP instruction 1 Group 131 pm_fpu_misc3
PM_FPU_ST_FOLDED_GRP131 FPU folded store 2 Group 131 pm_fpu_misc3
PM_FPU_FEST_GRP131 FPU executed FEST instruction 3 Group 131 pm_fpu_misc3
PM_PURR_GRP132 PURR Event 0 Group 132 pm_purr
PM_RUN_CYC_GRP132 Run cycles 1 Group 132 pm_purr
PM_CYC_GRP132 Processor cycles 2 Group 132 pm_purr
PM_INST_CMPL_GRP132 Instructions completed 3 Group 132 pm_purr
PM_SUSPENDED_GRP133 Suspended 0 Group 133 pm_suspend
PM_CYC_GRP133 Processor cycles 1 Group 133 pm_suspend
PM_SYNC_CYC_GRP133 Sync duration 2 Group 133 pm_suspend
PM_INST_CMPL_GRP133 Instructions completed 3 Group 133 pm_suspend
PM_LD_MISS_L1_CYC_GRP134 L1 data load miss cycles 0 Group 134 pm_dcache
PM_LSU_DERAT_MISS_GRP134 DERAT misses 1 Group 134 pm_dcache
PM_LD_MISS_L1_GRP134 L1 D cache load misses 2 Group 134 pm_dcache
PM_LSU_DERAT_MISS_CYC_GRP134 DERAT miss latency 3 Group 134 pm_dcache
PM_DERAT_MISS_4K_GRP135 DERAT misses for 4K page 0 Group 135 pm_derat_miss
PM_DERAT_MISS_64K_GRP135 DERAT misses for 64K page 1 Group 135 pm_derat_miss
PM_DERAT_MISS_16M_GRP135 DERAT misses for 16M page 2 Group 135 pm_derat_miss
PM_DERAT_MISS_16G_GRP135 DERAT misses for 16G page 3 Group 135 pm_derat_miss
PM_DERAT_REF_4K_GRP136 DERAT reference for 4K page 0 Group 136 pm_derat_ref
PM_DERAT_REF_64K_GRP136 DERAT reference for 64K page 1 Group 136 pm_derat_ref
PM_DERAT_REF_16M_GRP136 DERAT reference for 16M page 2 Group 136 pm_derat_ref
PM_DERAT_REF_16G_GRP136 DERAT reference for 16G page 3 Group 136 pm_derat_ref
PM_IERAT_MISS_16G_GRP137 IERAT misses for 16G page 0 Group 137 pm_ierat_miss
PM_IERAT_MISS_16M_GRP137 IERAT misses for 16M page 1 Group 137 pm_ierat_miss
PM_IERAT_MISS_64K_GRP137 IERAT misses for 64K page 2 Group 137 pm_ierat_miss
PM_IERAT_MISS_4K_GRP137 IERAT misses for 4K page 3 Group 137 pm_ierat_miss
PM_MRK_BR_TAKEN_GRP138 Marked branch taken 0 Group 138 pm_mrk_br
PM_MRK_LD_MISS_L1_GRP138 Marked L1 D cache load misses 1 Group 138 pm_mrk_br
PM_MRK_BR_MPRED_GRP138 Marked branch mispredicted 2 Group 138 pm_mrk_br
PM_INST_CMPL_GRP138 Instructions completed 3 Group 138 pm_mrk_br
PM_INST_CMPL_GRP139 Instructions completed 0 Group 139 pm_mrk_dsource
PM_MRK_DATA_FROM_DMEM_GRP139 Marked data loaded from distant memory 1 Group 139 pm_mrk_dsource
PM_MRK_DATA_FROM_DL2L3_SHR_GRP139 Marked data loaded from distant L2 or L3 shared 2 Group 139 pm_mrk_dsource
PM_MRK_DATA_FROM_DL2L3_MOD_GRP139 Marked data loaded from distant L2 or L3 modified 3 Group 139 pm_mrk_dsource
PM_MRK_DATA_FROM_L2_GRP140 Marked data loaded from L2 0 Group 140 pm_mrk_dsource2
PM_MRK_DATA_FROM_L21_GRP140 Marked data loaded from private L2 other core 1 Group 140 pm_mrk_dsource2
PM_MRK_DATA_FROM_L25_MOD_GRP140 Marked data loaded from L2.5 modified 2 Group 140 pm_mrk_dsource2
PM_INST_CMPL_GRP140 Instructions completed 3 Group 140 pm_mrk_dsource2
PM_MRK_DATA_FROM_L2MISS_GRP141 Marked data loaded missed L2 0 Group 141 pm_mrk_dsource3
PM_INST_CMPL_GRP141 Instructions completed 1 Group 141 pm_mrk_dsource3
PM_MRK_DATA_FROM_L3_GRP141 Marked data loaded from L3 2 Group 141 pm_mrk_dsource3
PM_MRK_DATA_FROM_L25_SHR_GRP141 Marked data loaded from L2.5 shared 3 Group 141 pm_mrk_dsource3
PM_MRK_DATA_FROM_L35_MOD_GRP142 Marked data loaded from L3.5 modified 0 Group 142 pm_mrk_dsource4
PM_MRK_DATA_FROM_L35_SHR_GRP142 Marked data loaded from L3.5 shared 1 Group 142 pm_mrk_dsource4
PM_MRK_DATA_FROM_L3MISS_GRP142 Marked data loaded from L3 miss 2 Group 142 pm_mrk_dsource4
PM_INST_CMPL_GRP142 Instructions completed 3 Group 142 pm_mrk_dsource4
PM_MRK_DATA_FROM_MEM_DP_GRP143 Marked data loaded from double pump memory 0 Group 143 pm_mrk_dsource5
PM_MRK_DATA_FROM_RL2L3_SHR_GRP143 Marked data loaded from remote L2 or L3 shared 1 Group 143 pm_mrk_dsource5
PM_INST_CMPL_GRP143 Instructions completed 2 Group 143 pm_mrk_dsource5
PM_MRK_DATA_FROM_LMEM_GRP143 Marked data loaded from local memory 3 Group 143 pm_mrk_dsource5
PM_MRK_DATA_FROM_RL2L3_MOD_GRP144 Marked data loaded from remote L2 or L3 modified 0 Group 144 pm_mrk_dsource6
PM_MRK_DATA_FROM_RL2L3_SHR_GRP144 Marked data loaded from remote L2 or L3 shared 1 Group 144 pm_mrk_dsource6
PM_MRK_DATA_FROM_RMEM_GRP144 Marked data loaded from remote memory 2 Group 144 pm_mrk_dsource6
PM_INST_CMPL_GRP144 Instructions completed 3 Group 144 pm_mrk_dsource6
PM_MRK_LSU_REJECT_ULD_GRP145 Marked unaligned load reject 0 Group 145 pm_mrk_rejects
PM_MRK_LSU_REJECT_UST_GRP145 Marked unaligned store reject 1 Group 145 pm_mrk_rejects
PM_INST_CMPL_GRP145 Instructions completed 2 Group 145 pm_mrk_rejects
PM_MRK_LSU_REJECT_LHS_GRP145 Marked load hit store reject 3 Group 145 pm_mrk_rejects
PM_MRK_LSU0_REJECT_LHS_GRP146 LSU0 marked load hit store reject 0 Group 146 pm_mrk_rejects2
PM_MRK_LSU0_REJECT_ULD_GRP146 LSU0 marked unaligned load reject 1 Group 146 pm_mrk_rejects2
PM_MRK_LSU0_REJECT_UST_GRP146 LSU0 marked unaligned store reject 2 Group 146 pm_mrk_rejects2
PM_INST_CMPL_GRP146 Instructions completed 3 Group 146 pm_mrk_rejects2
PM_MRK_LSU1_REJECT_LHS_GRP147 LSU1 marked load hit store reject 0 Group 147 pm_mrk_rejects3
PM_MRK_LSU1_REJECT_ULD_GRP147 LSU1 marked unaligned load reject 1 Group 147 pm_mrk_rejects3
PM_MRK_LSU1_REJECT_UST_GRP147 LSU1 marked unaligned store reject 2 Group 147 pm_mrk_rejects3
PM_INST_CMPL_GRP147 Instructions completed 3 Group 147 pm_mrk_rejects3
PM_MRK_INST_ISSUED_GRP148 Marked instruction issued 0 Group 148 pm_mrk_inst
PM_MRK_INST_DISP_GRP148 Marked instruction dispatched 1 Group 148 pm_mrk_inst
PM_MRK_INST_FIN_GRP148 Marked instruction finished 2 Group 148 pm_mrk_inst
PM_INST_CMPL_GRP148 Instructions completed 3 Group 148 pm_mrk_inst
PM_MRK_FPU0_FIN_GRP149 Marked instruction FPU0 processing finished 0 Group 149 pm_mrk_fpu_fin
PM_MRK_FPU1_FIN_GRP149 Marked instruction FPU1 processing finished 1 Group 149 pm_mrk_fpu_fin
PM_MRK_FPU_FIN_GRP149 Marked instruction FPU processing finished 2 Group 149 pm_mrk_fpu_fin
PM_INST_CMPL_GRP149 Instructions completed 3 Group 149 pm_mrk_fpu_fin
PM_MRK_LSU_REJECT_ULD_GRP150 Marked unaligned load reject 0 Group 150 pm_mrk_misc
PM_MRK_FXU_FIN_GRP150 Marked instruction FXU processing finished 1 Group 150 pm_mrk_misc
PM_MRK_DFU_FIN_GRP150 DFU marked instruction finish 2 Group 150 pm_mrk_misc
PM_INST_CMPL_GRP150 Instructions completed 3 Group 150 pm_mrk_misc
PM_MRK_STCX_FAIL_GRP151 Marked STCX failed 0 Group 151 pm_mrk_misc2
PM_MRK_IFU_FIN_GRP151 Marked instruction IFU processing finished 1 Group 151 pm_mrk_misc2
PM_INST_CMPL_GRP151 Instructions completed 2 Group 151 pm_mrk_misc2
PM_MRK_INST_TIMEO_GRP151 Marked Instruction finish timeout 3 Group 151 pm_mrk_misc2
PM_MRK_VMX_ST_ISSUED_GRP152 Marked VMX store issued 0 Group 152 pm_mrk_misc3
PM_MRK_LSU0_REJECT_L2MISS_GRP152 LSU0 marked L2 miss reject 1 Group 152 pm_mrk_misc3
PM_INST_CMPL_GRP152 Instructions completed 2 Group 152 pm_mrk_misc3
PM_MRK_LSU_DERAT_MISS_GRP152 Marked DERAT miss 3 Group 152 pm_mrk_misc3
PM_CYC_GRP153 Processor cycles 0 Group 153 pm_mrk_misc4
PM_CYC_GRP153 Processor cycles 1 Group 153 pm_mrk_misc4
PM_INST_CMPL_GRP153 Instructions completed 2 Group 153 pm_mrk_misc4
PM_MRK_LSU_FIN_GRP153 Marked instruction LSU processing finished 3 Group 153 pm_mrk_misc4
PM_MRK_ST_CMPL_GRP154 Marked store instruction completed 0 Group 154 pm_mrk_st
PM_MRK_ST_GPS_GRP154 Marked store sent to GPS 1 Group 154 pm_mrk_st
PM_MRK_ST_CMPL_INT_GRP154 Marked store completed with intervention 2 Group 154 pm_mrk_st
PM_INST_CMPL_GRP154 Instructions completed 3 Group 154 pm_mrk_st
PM_MRK_PTEG_FROM_L2_GRP155 Marked PTEG loaded from L2.5 modified 0 Group 155 pm_mrk_pteg
PM_MRK_PTEG_FROM_DMEM_GRP155 Marked PTEG loaded from distant memory 1 Group 155 pm_mrk_pteg
PM_MRK_PTEG_FROM_DL2L3_SHR_GRP155 Marked PTEG loaded from distant L2 or L3 shared 2 Group 155 pm_mrk_pteg
PM_INST_CMPL_GRP155 Instructions completed 3 Group 155 pm_mrk_pteg
PM_INST_CMPL_GRP156 Instructions completed 0 Group 156 pm_mrk_pteg2
PM_MRK_PTEG_FROM_L21_GRP156 Marked PTEG loaded from private L2 other core 1 Group 156 pm_mrk_pteg2
PM_MRK_PTEG_FROM_L25_MOD_GRP156 Marked PTEG loaded from L2.5 modified 2 Group 156 pm_mrk_pteg2
PM_MRK_PTEG_FROM_DL2L3_MOD_GRP156 Marked PTEG loaded from distant L2 or L3 modified 3 Group 156 pm_mrk_pteg2
PM_MRK_PTEG_FROM_L35_MOD_GRP157 Marked PTEG loaded from L3.5 modified 0 Group 157 pm_mrk_pteg3
PM_MRK_PTEG_FROM_L35_SHR_GRP157 Marked PTEG loaded from L3.5 shared 1 Group 157 pm_mrk_pteg3
PM_INST_CMPL_GRP157 Instructions completed 2 Group 157 pm_mrk_pteg3
PM_MRK_PTEG_FROM_L25_SHR_GRP157 Marked PTEG loaded from L2.5 shared 3 Group 157 pm_mrk_pteg3
PM_MRK_PTEG_FROM_MEM_DP_GRP158 Marked PTEG loaded from double pump memory 0 Group 158 pm_mrk_pteg4
PM_INST_CMPL_GRP158 Instructions completed 1 Group 158 pm_mrk_pteg4
PM_MRK_PTEG_FROM_L3_GRP158 Marked PTEG loaded from L3 2 Group 158 pm_mrk_pteg4
PM_MRK_PTEG_FROM_L2MISS_GRP158 Marked PTEG loaded from L2 miss 3 Group 158 pm_mrk_pteg4
PM_MRK_PTEG_FROM_RL2L3_MOD_GRP159 Marked PTEG loaded from remote L2 or L3 modified 0 Group 159 pm_mrk_pteg5
PM_INST_CMPL_GRP159 Instructions completed 1 Group 159 pm_mrk_pteg5
PM_MRK_PTEG_FROM_L3MISS_GRP159 Marked PTEG loaded from L3 miss 2 Group 159 pm_mrk_pteg5
PM_MRK_PTEG_FROM_LMEM_GRP159 Marked PTEG loaded from local memory 3 Group 159 pm_mrk_pteg5
PM_CYC_GRP160 Processor cycles 0 Group 160 pm_mrk_pteg6
PM_MRK_PTEG_FROM_RL2L3_SHR_GRP160 Marked PTEG loaded from remote L2 or L3 shared 1 Group 160 pm_mrk_pteg6
PM_MRK_PTEG_FROM_RMEM_GRP160 Marked PTEG loaded from remote memory 2 Group 160 pm_mrk_pteg6
PM_INST_CMPL_GRP160 Instructions completed 3 Group 160 pm_mrk_pteg6
PM_MRK_VMX_COMPLEX_ISSUED_GRP161 Marked VMX instruction issued to complex 0 Group 161 pm_mrk_vmx
PM_MRK_VMX_FLOAT_ISSUED_GRP161 Marked VMX instruction issued to float 1 Group 161 pm_mrk_vmx
PM_MRK_VMX_PERMUTE_ISSUED_GRP161 Marked VMX instruction issued to permute 2 Group 161 pm_mrk_vmx
PM_INST_CMPL_GRP161 Instructions completed 3 Group 161 pm_mrk_vmx
PM_MRK_VMX0_LD_WRBACK_GRP162 Marked VMX0 load writeback valid 0 Group 162 pm_mrk_vmx2
PM_MRK_VMX1_LD_WRBACK_GRP162 Marked VMX1 load writeback valid 1 Group 162 pm_mrk_vmx2
PM_MRK_DTLB_REF_GRP162 Marked Data TLB reference 2 Group 162 pm_mrk_vmx2
PM_INST_CMPL_GRP162 Instructions completed 3 Group 162 pm_mrk_vmx2
PM_MRK_VMX_SIMPLE_ISSUED_GRP163 Marked VMX instruction issued to simple 0 Group 163 pm_mrk_vmx3
PM_VMX_SIMPLE_ISSUED_GRP163 VMX instruction issued to simple 1 Group 163 pm_mrk_vmx3
PM_CYC_GRP163 Processor cycles 2 Group 163 pm_mrk_vmx3
PM_INST_CMPL_GRP163 Instructions completed 3 Group 163 pm_mrk_vmx3
PM_MRK_FPU0_FIN_GRP164 Marked instruction FPU0 processing finished 0 Group 164 pm_mrk_fp
PM_MRK_FPU_FIN_GRP164 Marked instruction FPU processing finished 1 Group 164 pm_mrk_fp
PM_MRK_FPU1_FIN_GRP164 Marked instruction FPU1 processing finished 2 Group 164 pm_mrk_fp
PM_INST_CMPL_GRP164 Instructions completed 3 Group 164 pm_mrk_fp
PM_MRK_DERAT_REF_64K_GRP165 Marked DERAT reference for 64K page 0 Group 165 pm_mrk_derat_ref
PM_MRK_DERAT_REF_4K_GRP165 Marked DERAT reference for 4K page 1 Group 165 pm_mrk_derat_ref
PM_MRK_DERAT_REF_16M_GRP165 Marked DERAT reference for 16M page 2 Group 165 pm_mrk_derat_ref
PM_INST_CMPL_GRP165 Instructions completed 3 Group 165 pm_mrk_derat_ref
PM_MRK_DERAT_MISS_64K_GRP166 Marked DERAT misses for 64K page 0 Group 166 pm_mrk_derat_miss
PM_MRK_DERAT_MISS_4K_GRP166 Marked DERAT misses for 4K page 1 Group 166 pm_mrk_derat_miss
PM_MRK_DERAT_MISS_16M_GRP166 Marked DERAT misses for 16M page 2 Group 166 pm_mrk_derat_miss
PM_INST_CMPL_GRP166 Instructions completed 3 Group 166 pm_mrk_derat_miss
PM_LD_MISS_L1_GRP167 L1 D cache load misses 0 Group 167 pm_dcache_edge
PM_LSU_DERAT_MISS_GRP167 DERAT misses 1 Group 167 pm_dcache_edge
PM_LD_MISS_L1_GRP167 L1 D cache load misses 2 Group 167 pm_dcache_edge
PM_LSU_DERAT_MISS_GRP167 DERAT misses 3 Group 167 pm_dcache_edge
PM_LSU_LMQ_FULL_CYC_GRP168 Cycles LMQ full 0 Group 168 pm_lsu_lmq_edge
PM_LSU_LMQ_SRQ_EMPTY_COUNT_GRP168 Periods LMQ and SRQ empty 1 Group 168 pm_lsu_lmq_edge
PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT_GRP168 Periods both threads LMQ and SRQ empty 2 Group 168 pm_lsu_lmq_edge
PM_LSU0_REJECT_L2MISS_GRP168 LSU0 L2 miss reject 3 Group 168 pm_lsu_lmq_edge
PM_GCT_NOSLOT_COUNT_GRP169 Periods no GCT slot allocated 0 Group 169 pm_gct_edge
PM_GCT_EMPTY_COUNT_GRP169 Periods GCT empty 1 Group 169 pm_gct_edge
PM_GCT_FULL_COUNT_GRP169 Periods GCT full 2 Group 169 pm_gct_edge
PM_INST_FETCH_CYC_GRP169 Cycles at least 1 instruction fetched 3 Group 169 pm_gct_edge
PM_DPU_HELD_THERMAL_COUNT_GRP170 Periods DISP unit held due to thermal condition 0 Group 170 pm_freq_edge
PM_DPU_HELD_POWER_COUNT_GRP170 Periods DISP unit held due to Power Management 1 Group 170 pm_freq_edge
PM_FREQ_DOWN_GRP170 Frequency is being slewed down due to Power Management 2 Group 170 pm_freq_edge
PM_FREQ_UP_GRP170 Frequency is being slewed up due to Power Management 3 Group 170 pm_freq_edge
PM_L1_ICACHE_MISS_GRP171 L1 I cache miss count 0 Group 171 pm_disp_wait_edge
PM_DPU_WT_IC_MISS_COUNT_GRP171 Periods DISP unit is stalled due to I cache miss 1 Group 171 pm_disp_wait_edge
PM_DPU_WT_COUNT_GRP171 Periods DISP unit is stalled waiting for instructions 2 Group 171 pm_disp_wait_edge
PM_DPU_WT_BR_MPRED_COUNT_GRP171 Periods DISP unit is stalled due to branch misprediction 3 Group 171 pm_disp_wait_edge
PM_LD_MISS_L1_GRP172 L1 D cache load misses 0 Group 172 pm_edge1
PM_DPU_WT_IC_MISS_GRP172 Cycles DISP unit is stalled due to I cache miss 1 Group 172 pm_edge1
PM_LLA_COUNT_GRP172 Transitions into Load Look Ahead mode 2 Group 172 pm_edge1
PM_LLA_CYC_GRP172 Load Look Ahead Active 3 Group 172 pm_edge1
PM_0INST_FETCH_COUNT_GRP173 Periods with no instructions fetched 0 Group 173 pm_edge2
PM_0INST_FETCH_GRP173 No instructions fetched 1 Group 173 pm_edge2
PM_IBUF_FULL_COUNT_GRP173 Periods instruction buffer full 2 Group 173 pm_edge2
PM_IBUF_FULL_CYC_GRP173 Cycles instruction buffer full 3 Group 173 pm_edge2
PM_RUN_COUNT_GRP174 Run Periods 0 Group 174 pm_edge3
PM_RUN_CYC_GRP174 Run cycles 1 Group 174 pm_edge3
PM_INST_TABLEWALK_COUNT_GRP174 Periods doing instruction tablewalks 2 Group 174 pm_edge3
PM_INST_TABLEWALK_CYC_GRP174 Cycles doing instruction tablewalks 3 Group 174 pm_edge3
PM_GCT_FULL_COUNT_GRP175 Periods GCT full 0 Group 175 pm_edge4
PM_GCT_FULL_CYC_GRP175 Cycles GCT full 1 Group 175 pm_edge4
PM_NO_ITAG_COUNT_GRP175 Periods no ITAG available 2 Group 175 pm_edge4
PM_NO_ITAG_CYC_GRP175 Cyles no ITAG available 3 Group 175 pm_edge4
PM_THRD_ONE_RUN_COUNT_GRP176 Periods one of the threads in run cycles 0 Group 176 pm_edge5
PM_HV_COUNT_GRP176 Hypervisor Periods 1 Group 176 pm_edge5
PM_SYNC_COUNT_GRP176 SYNC instructions completed 2 Group 176 pm_edge5
PM_SYNC_CYC_GRP176 Sync duration 3 Group 176 pm_edge5
PM_THRD_ONE_RUN_CYC_GRP177 One of the threads in run cycles 0 Group 177 pm_noedge5
PM_HV_CYC_GRP177 Hypervisor Cycles 1 Group 177 pm_noedge5
PM_SYNC_COUNT_GRP177 SYNC instructions completed 2 Group 177 pm_noedge5
PM_SYNC_CYC_GRP177 Sync duration 3 Group 177 pm_noedge5
PM_DPU_HELD_THERMAL_COUNT_GRP178 Periods DISP unit held due to thermal condition 0 Group 178 pm_edge6
PM_DPU_HELD_COUNT_GRP178 Periods DISP unit held 1 Group 178 pm_edge6
PM_DPU_WT_COUNT_GRP178 Periods DISP unit is stalled waiting for instructions 2 Group 178 pm_edge6
PM_DPU_WT_BR_MPRED_COUNT_GRP178 Periods DISP unit is stalled due to branch misprediction 3 Group 178 pm_edge6
PM_DPU_HELD_THERMAL_GRP179 DISP unit held due to thermal condition 0 Group 179 pm_noedge6
PM_DPU_HELD_GRP179 DISP unit held 1 Group 179 pm_noedge6
PM_DPU_WT_GRP179 Cycles DISP unit is stalled waiting for instructions 2 Group 179 pm_noedge6
PM_DPU_WT_BR_MPRED_GRP179 Cycles DISP unit is stalled due to branch misprediction 3 Group 179 pm_noedge6
PM_GCT_NOSLOT_COUNT_GRP180 Periods no GCT slot allocated 0 Group 180 pm_edge7
PM_GCT_EMPTY_COUNT_GRP180 Periods GCT empty 1 Group 180 pm_edge7
PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT_GRP180 Periods both threads LMQ and SRQ empty 2 Group 180 pm_edge7
PM_LSU_SRQ_EMPTY_COUNT_GRP180 Periods SRQ empty 3 Group 180 pm_edge7
PM_GCT_NOSLOT_CYC_GRP181 Cycles no GCT slot allocated 0 Group 181 pm_noedge7
PM_GCT_EMPTY_CYC_GRP181 Cycles GCT empty 1 Group 181 pm_noedge7
PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC_GRP181 Cycles both threads LMQ and SRQ empty 2 Group 181 pm_noedge7
PM_LSU_SRQ_EMPTY_CYC_GRP181 Cycles SRQ empty 3 Group 181 pm_noedge7
PM_SYNC_COUNT_GRP182 SYNC instructions completed 0 Group 182 pm_edge8
PM_LSU_LMQ_SRQ_EMPTY_COUNT_GRP182 Periods LMQ and SRQ empty 1 Group 182 pm_edge8
PM_SYNC_CYC_GRP182 Sync duration 2 Group 182 pm_edge8
PM_LSU_DERAT_MISS_GRP182 DERAT misses 3 Group 182 pm_edge8
PM_SYNC_CYC_GRP183 Sync duration 0 Group 183 pm_noedge8
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP183 Cycles LMQ and SRQ empty 1 Group 183 pm_noedge8
PM_SYNC_COUNT_GRP183 SYNC instructions completed 2 Group 183 pm_noedge8
PM_LSU_DERAT_MISS_CYC_GRP183 DERAT miss latency 3 Group 183 pm_noedge8
PM_ST_MISS_L1_GRP184 L1 D cache store misses 0 Group 184 pm_edge9
PM_DPU_WT_IC_MISS_COUNT_GRP184 Periods DISP unit is stalled due to I cache miss 1 Group 184 pm_edge9
PM_LD_MISS_L1_GRP184 L1 D cache load misses 2 Group 184 pm_edge9
PM_LD_REF_L1_GRP184 L1 D cache load references 3 Group 184 pm_edge9
PM_DPU_HELD_COMPLETION_GRP185 DISP unit held due to completion holding dispatch 0 Group 185 pm_edge10
PM_DPU_HELD_POWER_COUNT_GRP185 Periods DISP unit held due to Power Management 1 Group 185 pm_edge10
PM_DPU_HELD_CR_LOGICAL_GRP185 DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR 2 Group 185 pm_edge10
PM_THRD_BOTH_RUN_COUNT_GRP185 Periods both threads in run cycles 3 Group 185 pm_edge10
PM_DPU_HELD_COMPLETION_GRP186 DISP unit held due to completion holding dispatch 0 Group 186 pm_noedge10
PM_DPU_HELD_POWER_GRP186 DISP unit held due to Power Management 1 Group 186 pm_noedge10
PM_DPU_HELD_CR_LOGICAL_GRP186 DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR 2 Group 186 pm_noedge10
PM_THRD_BOTH_RUN_CYC_GRP186 Both threads in run cycles 3 Group 186 pm_noedge10
PM_FPU_1FLOP_GRP187 FPU executed one flop instruction 0 Group 187 pm_hpm1
PM_FPU_FMA_GRP187 FPU executed multiply-add instruction 1 Group 187 pm_hpm1
PM_FPU_FSQRT_FDIV_GRP187 FPU executed FSQRT or FDIV instruction 2 Group 187 pm_hpm1
PM_CYC_GRP187 Processor cycles 3 Group 187 pm_hpm1
PM_INST_CMPL_GRP188 Instructions completed 0 Group 188 pm_hpm2
PM_LSU_LDF_GRP188 LSU executed Floating Point load instruction 1 Group 188 pm_hpm2
PM_FPU_STF_GRP188 FPU executed store instruction 2 Group 188 pm_hpm2
PM_CYC_GRP188 Processor cycles 3 Group 188 pm_hpm2
PM_CYC_GRP189 Processor cycles 0 Group 189 pm_hpm3
PM_LD_MISS_L1_GRP189 L1 D cache load misses 1 Group 189 pm_hpm3
PM_ST_MISS_L1_GRP189 L1 D cache store misses 2 Group 189 pm_hpm3
PM_INST_CMPL_GRP189 Instructions completed 3 Group 189 pm_hpm3
PM_INST_CMPL_GRP190 Instructions completed 0 Group 190 pm_hpm4
PM_INST_DISP_GRP190 Instructions dispatched 1 Group 190 pm_hpm4
PM_LD_REF_L1_GRP190 L1 D cache load references 2 Group 190 pm_hpm4
PM_ST_REF_L1_GRP190 L1 D cache store references 3 Group 190 pm_hpm4
PM_FPU_FIN_GRP191 FPU produced a result 0 Group 191 pm_hpm5
PM_CYC_GRP191 Processor cycles 1 Group 191 pm_hpm5
PM_FXU0_FIN_GRP191 FXU0 produced a result 2 Group 191 pm_hpm5
PM_FXU1_FIN_GRP191 FXU1 produced a result 3 Group 191 pm_hpm5
PM_DATA_FROM_L2_GRP192 Data loaded from L2 0 Group 192 pm_hpm6
PM_DATA_FROM_L21_GRP192 Data loaded from private L2 other core 1 Group 192 pm_hpm6
PM_DATA_FROM_L25_MOD_GRP192 Data loaded from L2.5 modified 2 Group 192 pm_hpm6
PM_DATA_FROM_L25_SHR_GRP192 Data loaded from L2.5 shared 3 Group 192 pm_hpm6
PM_DATA_FROM_L35_MOD_GRP193 Data loaded from L3.5 modified 0 Group 193 pm_hpm7
PM_DATA_FROM_L35_SHR_GRP193 Data loaded from L3.5 shared 1 Group 193 pm_hpm7
PM_DATA_FROM_L3_GRP193 Data loaded from L3 2 Group 193 pm_hpm7
PM_CYC_GRP193 Processor cycles 3 Group 193 pm_hpm7
PM_FPU_1FLOP_GRP194 FPU executed one flop instruction 0 Group 194 pm_hpm8
PM_FPU_FMA_GRP194 FPU executed multiply-add instruction 1 Group 194 pm_hpm8
PM_FPU_STF_GRP194 FPU executed store instruction 2 Group 194 pm_hpm8
PM_LD_MISS_L1_GRP194 L1 D cache load misses 3 Group 194 pm_hpm8
PM_LD_MISS_L1_GRP195 L1 D cache load misses 0 Group 195 pm_hpm9
PM_CYC_GRP195 Processor cycles 1 Group 195 pm_hpm9
PM_LSU_LDF_GRP195 LSU executed Floating Point load instruction 2 Group 195 pm_hpm9
PM_ST_MISS_L1_GRP195 L1 D cache store misses 3 Group 195 pm_hpm9
PM_INST_CMPL_GRP196 Instructions completed 0 Group 196 pm_hpm10
PM_L2_MISS_GRP196 L2 cache misses 1 Group 196 pm_hpm10
PM_INST_FROM_L3MISS_GRP196 Instruction fetched missed L3 2 Group 196 pm_hpm10
PM_DATA_FROM_L3MISS_GRP196 Data loaded from private L3 miss 3 Group 196 pm_hpm10
PM_MRK_DERAT_REF_64K_GRP197 Marked DERAT reference for 64K page 0 Group 197 pm_mrk_derat_ref2
PM_MRK_DERAT_REF_4K_GRP197 Marked DERAT reference for 4K page 1 Group 197 pm_mrk_derat_ref2
PM_INST_CMPL_GRP197 Instructions completed 2 Group 197 pm_mrk_derat_ref2
PM_MRK_DERAT_REF_16G_GRP197 Marked DERAT reference for 16G page 3 Group 197 pm_mrk_derat_ref2
PM_MRK_DERAT_MISS_64K_GRP198 Marked DERAT misses for 64K page 0 Group 198 pm_mrk_derat_miss2
PM_MRK_DERAT_MISS_4K_GRP198 Marked DERAT misses for 4K page 1 Group 198 pm_mrk_derat_miss2
PM_INST_CMPL_GRP198 Instructions completed 2 Group 198 pm_mrk_derat_miss2
PM_MRK_DERAT_MISS_16G_GRP198 Marked DERAT misses for 16G page 3 Group 198 pm_mrk_derat_miss2
A wise man proportions his belief to the evidence. - David Hume
2014/09/12