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ppc64 POWER7 events

This is a list of all ppc64 POWER7's performance counter event types.

NameDescriptionCounters usableGroup
CYCLES Processor Cycles 0
PM_CYC_GRP1 Processor Cycles 0 Group 1 pm_utilization
PM_RUN_CYC_GRP1 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 1 pm_utilization
PM_INST_DISP_GRP1 Number of PowerPC instructions successfully dispatched. 2 Group 1 pm_utilization
PM_INST_CMPL_GRP1 Number of PowerPC Instructions that completed. 3 Group 1 pm_utilization
PM_RUN_INST_CMPL_GRP1 Number of run instructions completed. 4 Group 1 pm_utilization
PM_RUN_CYC_GRP1 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 1 pm_utilization
PM_BR_PRED_CCACHE_GRP2 The count value of a Branch and Count instruction was predicted 0 Group 2 pm_branch1
PM_BR_PRED_LSTACK_GRP2 The target address of a Branch to Link instruction was predicted by the link stack. 1 Group 2 pm_branch1
PM_BR_MPRED_CCACHE_GRP2 A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. 2 Group 2 pm_branch1
PM_BR_MPRED_TA_GRP2 A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. 3 Group 2 pm_branch1
PM_RUN_INST_CMPL_GRP2 Number of run instructions completed. 4 Group 2 pm_branch1
PM_RUN_CYC_GRP2 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 2 pm_branch1
PM_BR_PRED_GRP3 A branch prediction was made. This could have been a target prediction, a condition prediction, or both 0 Group 3 pm_branch2
PM_BR_PRED_CR_GRP3 A conditional branch instruction was predicted as taken or not taken. 1 Group 3 pm_branch2
PM_BR_PRED_CCACHE_GRP3 The count value of a Branch and Count instruction was predicted 2 Group 3 pm_branch2
PM_BR_PRED_LSTACK_GRP3 The target address of a Branch to Link instruction was predicted by the link stack. 3 Group 3 pm_branch2
PM_RUN_INST_CMPL_GRP3 Number of run instructions completed. 4 Group 3 pm_branch2
PM_RUN_CYC_GRP3 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 3 pm_branch2
PM_BRU_FIN_GRP4 The Branch execution unit finished an instruction 0 Group 4 pm_branch3
PM_BR_TAKEN_GRP4 A branch instruction was taken. This could have been a conditional branch or an unconditional branch 1 Group 4 pm_branch3
PM_BR_PRED_GRP4 A branch prediction was made. This could have been a target prediction, a condition prediction, or both 2 Group 4 pm_branch3
PM_BR_MPRED_GRP4 A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both 3 Group 4 pm_branch3
PM_RUN_INST_CMPL_GRP4 Number of run instructions completed. 4 Group 4 pm_branch3
PM_RUN_CYC_GRP4 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 4 pm_branch3
PM_BR_MPRED_CR_GRP5 A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction. 0 Group 5 pm_branch4
PM_BR_UNCOND_GRP5 An unconditional branch was executed. 1 Group 5 pm_branch4
PM_BR_MPRED_TA_GRP5 A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. 2 Group 5 pm_branch4
PM_BR_MPRED_CCACHE_GRP5 A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. 3 Group 5 pm_branch4
PM_RUN_INST_CMPL_GRP5 Number of run instructions completed. 4 Group 5 pm_branch4
PM_RUN_CYC_GRP5 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 5 pm_branch4
PM_BR_PRED_CR_TA_GRP6 Both the condition (taken or not taken) and the target address of a branch instruction was predicted. 0 Group 6 pm_branch5
PM_BR_MPRED_CR_TA_GRP6 Branch mispredict - taken/not taken and target 1 Group 6 pm_branch5
PM_BR_PRED_GRP6 A branch prediction was made. This could have been a target prediction, a condition prediction, or both 2 Group 6 pm_branch5
PM_BR_PRED_CR_GRP6 A conditional branch instruction was predicted as taken or not taken. 3 Group 6 pm_branch5
PM_RUN_INST_CMPL_GRP6 Number of run instructions completed. 4 Group 6 pm_branch5
PM_RUN_CYC_GRP6 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 6 pm_branch5
PM_BR_PRED_CCACHE_GRP7 The count value of a Branch and Count instruction was predicted 0 Group 7 pm_branch6
PM_BR_PRED_LSTACK_GRP7 The target address of a Branch to Link instruction was predicted by the link stack. 1 Group 7 pm_branch6
PM_BR_PRED_CR_GRP7 A conditional branch instruction was predicted as taken or not taken. 2 Group 7 pm_branch6
PM_BR_PRED_TA_GRP7 The target address of a branch instruction was predicted. 3 Group 7 pm_branch6
PM_RUN_INST_CMPL_GRP7 Number of run instructions completed. 4 Group 7 pm_branch6
PM_RUN_CYC_GRP7 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 7 pm_branch6
PM_BR_MPRED_CR_GRP8 A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction. 0 Group 8 pm_branch7
PM_BR_PRED_CR_GRP8 A conditional branch instruction was predicted as taken or not taken. 1 Group 8 pm_branch7
PM_BR_PRED_CCACHE_GRP8 The count value of a Branch and Count instruction was predicted 2 Group 8 pm_branch7
PM_BR_PRED_LSTACK_GRP8 The target address of a Branch to Link instruction was predicted by the link stack. 3 Group 8 pm_branch7
PM_RUN_INST_CMPL_GRP8 Number of run instructions completed. 4 Group 8 pm_branch7
PM_RUN_CYC_GRP8 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 8 pm_branch7
PM_BR_MPRED_TA_GRP9 A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. 0 Group 9 pm_branch8
PM_BR_PRED_CR_GRP9 A conditional branch instruction was predicted as taken or not taken. 1 Group 9 pm_branch8
PM_BR_PRED_CCACHE_GRP9 The count value of a Branch and Count instruction was predicted 2 Group 9 pm_branch8
PM_BR_PRED_LSTACK_GRP9 The target address of a Branch to Link instruction was predicted by the link stack. 3 Group 9 pm_branch8
PM_RUN_INST_CMPL_GRP9 Number of run instructions completed. 4 Group 9 pm_branch8
PM_RUN_CYC_GRP9 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 9 pm_branch8
PM_BR_MPRED_CCACHE_GRP10 A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. 0 Group 10 pm_branch9
PM_BR_PRED_CR_GRP10 A conditional branch instruction was predicted as taken or not taken. 1 Group 10 pm_branch9
PM_BR_PRED_CCACHE_GRP10 The count value of a Branch and Count instruction was predicted 2 Group 10 pm_branch9
PM_BR_PRED_LSTACK_GRP10 The target address of a Branch to Link instruction was predicted by the link stack. 3 Group 10 pm_branch9
PM_RUN_INST_CMPL_GRP10 Number of run instructions completed. 4 Group 10 pm_branch9
PM_RUN_CYC_GRP10 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 10 pm_branch9
PM_IERAT_MISS_GRP11 A translation request missed the Instruction Effective to Real Address Translation (ERAT) table 0 Group 11 pm_slb_miss
PM_DSLB_MISS_GRP11 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. 1 Group 11 pm_slb_miss
PM_ISLB_MISS_GRP11 A SLB miss for an instruction fetch as occurred 2 Group 11 pm_slb_miss
PM_SLB_MISS_GRP11 Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data. 3 Group 11 pm_slb_miss
PM_RUN_INST_CMPL_GRP11 Number of run instructions completed. 4 Group 11 pm_slb_miss
PM_RUN_CYC_GRP11 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 11 pm_slb_miss
PM_BTAC_MISS_GRP12 BTAC Mispredicted 0 Group 12 pm_tlb_miss
PM_TLB_MISS_GRP12 Total of Data TLB mises + Instruction TLB misses 1 Group 12 pm_tlb_miss
PM_DTLB_MISS_GRP12 Data TLB misses, all page sizes. 2 Group 12 pm_tlb_miss
PM_ITLB_MISS_GRP12 A TLB miss for an Instruction Fetch has occurred 3 Group 12 pm_tlb_miss
PM_RUN_INST_CMPL_GRP12 Number of run instructions completed. 4 Group 12 pm_tlb_miss
PM_RUN_CYC_GRP12 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 12 pm_tlb_miss
PM_DTLB_MISS_16G_GRP13 Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time. 0 Group 13 pm_dtlb_miss
PM_DTLB_MISS_4K_GRP13 Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time. 1 Group 13 pm_dtlb_miss
PM_DTLB_MISS_64K_GRP13 Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time. 2 Group 13 pm_dtlb_miss
PM_DTLB_MISS_16M_GRP13 Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time. 3 Group 13 pm_dtlb_miss
PM_RUN_INST_CMPL_GRP13 Number of run instructions completed. 4 Group 13 pm_dtlb_miss
PM_RUN_CYC_GRP13 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 13 pm_dtlb_miss
PM_DERAT_MISS_4K_GRP14 A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload. 0 Group 14 pm_derat_miss1
PM_DERAT_MISS_64K_GRP14 A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. 1 Group 14 pm_derat_miss1
PM_DERAT_MISS_16M_GRP14 A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. 2 Group 14 pm_derat_miss1
PM_DERAT_MISS_16G_GRP14 A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload. 3 Group 14 pm_derat_miss1
PM_RUN_INST_CMPL_GRP14 Number of run instructions completed. 4 Group 14 pm_derat_miss1
PM_RUN_CYC_GRP14 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 14 pm_derat_miss1
PM_INST_CMPL_GRP15 Number of PowerPC Instructions that completed. 0 Group 15 pm_derat_miss2
PM_DERAT_MISS_64K_GRP15 A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. 1 Group 15 pm_derat_miss2
PM_DERAT_MISS_16M_GRP15 A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. 2 Group 15 pm_derat_miss2
PM_DERAT_MISS_16G_GRP15 A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload. 3 Group 15 pm_derat_miss2
PM_RUN_INST_CMPL_GRP15 Number of run instructions completed. 4 Group 15 pm_derat_miss2
PM_RUN_CYC_GRP15 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 15 pm_derat_miss2
PM_DSLB_MISS_GRP16 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. 0 Group 16 pm_misc_miss1
PM_DATA_FROM_L2MISS_GRP16 The processor's Data Cache was reloaded but not from the local L2. 1 Group 16 pm_misc_miss1
PM_LSU_DERAT_MISS_GRP16 Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. 2 Group 16 pm_misc_miss1
PM_LD_MISS_L1_GRP16 Load references that miss the Level 1 Data cache. Combined unit 0 + 1. 3 Group 16 pm_misc_miss1
PM_RUN_INST_CMPL_GRP16 Number of run instructions completed. 4 Group 16 pm_misc_miss1
PM_RUN_CYC_GRP16 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 16 pm_misc_miss1
PM_CYC_GRP17 Processor Cycles 0 Group 17 pm_misc_miss2
PM_PTEG_FROM_L3MISS_GRP17 Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store. 1 Group 17 pm_misc_miss2
PM_LSU_DERAT_MISS_GRP17 Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. 2 Group 17 pm_misc_miss2
PM_RUN_INST_CMPL_GRP17 Number of run instructions completed. 3 Group 17 pm_misc_miss2
PM_RUN_INST_CMPL_GRP17 Number of run instructions completed. 4 Group 17 pm_misc_miss2
PM_RUN_CYC_GRP17 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 17 pm_misc_miss2
PM_CYC_GRP18 Processor Cycles 0 Group 18 pm_misc_miss3
PM_PTEG_FROM_L3MISS_GRP18 Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store. 1 Group 18 pm_misc_miss3
PM_LSU_DERAT_MISS_GRP18 Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. 2 Group 18 pm_misc_miss3
PM_PTEG_FROM_L2MISS_GRP18 A Page Table Entry was loaded into the TLB but not from the local L2. 3 Group 18 pm_misc_miss3
PM_RUN_INST_CMPL_GRP18 Number of run instructions completed. 4 Group 18 pm_misc_miss3
PM_RUN_CYC_GRP18 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 18 pm_misc_miss3
PM_DSLB_MISS_GRP19 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. 0 Group 19 pm_misc_miss4
PM_INST_FROM_L3MISS_GRP19 An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. 1 Group 19 pm_misc_miss4
PM_INST_CMPL_GRP19 Number of PowerPC Instructions that completed. 2 Group 19 pm_misc_miss4
PM_RUN_INST_CMPL_GRP19 Number of run instructions completed. 3 Group 19 pm_misc_miss4
PM_RUN_INST_CMPL_GRP19 Number of run instructions completed. 4 Group 19 pm_misc_miss4
PM_RUN_CYC_GRP19 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 19 pm_misc_miss4
PM_IERAT_MISS_GRP20 A translation request missed the Instruction Effective to Real Address Translation (ERAT) table 0 Group 20 pm_misc_miss5
PM_DSLB_MISS_GRP20 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. 1 Group 20 pm_misc_miss5
PM_ISLB_MISS_GRP20 A SLB miss for an instruction fetch as occurred 2 Group 20 pm_misc_miss5
PM_INST_CMPL_GRP20 Number of PowerPC Instructions that completed. 3 Group 20 pm_misc_miss5
PM_RUN_INST_CMPL_GRP20 Number of run instructions completed. 4 Group 20 pm_misc_miss5
PM_RUN_CYC_GRP20 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 20 pm_misc_miss5
PM_PTEG_FROM_L2_GRP21 A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store. 0 Group 21 pm_pteg1
PM_INST_PTEG_FROM_L3_GRP21 Instruction PTEG loaded from L3 1 Group 21 pm_pteg1
PM_PTEG_FROM_L21_MOD_GRP21 PTEG loaded from another L2 on same chip modified 2 Group 21 pm_pteg1
PM_INST_PTEG_FROM_DL2L3_MOD_GRP21 Instruction PTEG loaded from distant L2 or L3 modified 3 Group 21 pm_pteg1
PM_RUN_INST_CMPL_GRP21 Number of run instructions completed. 4 Group 21 pm_pteg1
PM_RUN_CYC_GRP21 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 21 pm_pteg1
PM_INST_PTEG_FROM_L2_GRP22 Instruction PTEG loaded from L2 0 Group 22 pm_pteg2
PM_INST_PTEG_FROM_RL2L3_SHR_GRP22 Instruction PTEG loaded from remote L2 or L3 shared 1 Group 22 pm_pteg2
PM_INST_PTEG_FROM_DL2L3_SHR_GRP22 Instruction PTEG loaded from remote L2 or L3 shared 2 Group 22 pm_pteg2
PM_PTEG_FROM_DL2L3_MOD_GRP22 A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store. 3 Group 22 pm_pteg2
PM_RUN_INST_CMPL_GRP22 Number of run instructions completed. 4 Group 22 pm_pteg2
PM_RUN_CYC_GRP22 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 22 pm_pteg2
PM_PTEG_FROM_L31_MOD_GRP23 PTEG loaded from another L3 on same chip modified 0 Group 23 pm_pteg3
PM_PTEG_FROM_L3MISS_GRP23 Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store. 1 Group 23 pm_pteg3
PM_INST_PTEG_FROM_RMEM_GRP23 Instruction PTEG loaded from remote memory 2 Group 23 pm_pteg3
PM_PTEG_FROM_LMEM_GRP23 A Page Table Entry was loaded into the TLB from memory attached to the same module this processor is located on. 3 Group 23 pm_pteg3
PM_RUN_INST_CMPL_GRP23 Number of run instructions completed. 4 Group 23 pm_pteg3
PM_RUN_CYC_GRP23 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 23 pm_pteg3
PM_INST_PTEG_FROM_RL2L3_MOD_GRP24 Instruction PTEG loaded from remote L2 or L3 modified 0 Group 24 pm_pteg4
PM_PTEG_FROM_DMEM_GRP24 A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store. 1 Group 24 pm_pteg4
PM_PTEG_FROM_RMEM_GRP24 A Page Table Entry was loaded into the TLB from memory attached to a different module than this processor is located on. 2 Group 24 pm_pteg4
PM_PTEG_FROM_LMEM_GRP24 A Page Table Entry was loaded into the TLB from memory attached to the same module this processor is located on. 3 Group 24 pm_pteg4
PM_RUN_INST_CMPL_GRP24 Number of run instructions completed. 4 Group 24 pm_pteg4
PM_RUN_CYC_GRP24 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 24 pm_pteg4
PM_PTEG_FROM_RL2L3_MOD_GRP25 A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store. 0 Group 25 pm_pteg5
PM_PTEG_FROM_L31_SHR_GRP25 PTEG loaded from another L3 on same chip shared 1 Group 25 pm_pteg5
PM_PTEG_FROM_DL2L3_SHR_GRP25 A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store. 2 Group 25 pm_pteg5
PM_PTEG_FROM_L21_SHR_GRP25 PTEG loaded from another L2 on same chip shared 3 Group 25 pm_pteg5
PM_RUN_INST_CMPL_GRP25 Number of run instructions completed. 4 Group 25 pm_pteg5
PM_RUN_CYC_GRP25 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 25 pm_pteg5
PM_INST_PTEG_FROM_L31_MOD_GRP26 Instruction PTEG loaded from another L3 on same chip modified 0 Group 26 pm_pteg6
PM_INST_PTEG_FROM_DMEM_GRP26 Instruction PTEG loaded from distant memory 1 Group 26 pm_pteg6
PM_INST_PTEG_FROM_L21_MOD_GRP26 Instruction PTEG loaded from another L2 on same chip modified 2 Group 26 pm_pteg6
PM_INST_PTEG_FROM_LMEM_GRP26 Instruction PTEG loaded from local memory 3 Group 26 pm_pteg6
PM_RUN_INST_CMPL_GRP26 Number of run instructions completed. 4 Group 26 pm_pteg6
PM_RUN_CYC_GRP26 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 26 pm_pteg6
PM_INST_PTEG_FROM_L31_MOD_GRP27 Instruction PTEG loaded from another L3 on same chip modified 0 Group 27 pm_pteg7
PM_INST_PTEG_FROM_L31_SHR_GRP27 Instruction PTEG loaded from another L3 on same chip shared 1 Group 27 pm_pteg7
PM_INST_PTEG_FROM_L21_MOD_GRP27 Instruction PTEG loaded from another L2 on same chip modified 2 Group 27 pm_pteg7
PM_INST_PTEG_FROM_L21_SHR_GRP27 Instruction PTEG loaded from another L2 on same chip shared 3 Group 27 pm_pteg7
PM_RUN_INST_CMPL_GRP27 Number of run instructions completed. 4 Group 27 pm_pteg7
PM_RUN_CYC_GRP27 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 27 pm_pteg7
PM_INST_PTEG_FROM_L2_GRP28 Instruction PTEG loaded from L2 0 Group 28 pm_pteg8
PM_INST_PTEG_FROM_L3MISS_GRP28 Instruction PTEG loaded from L3 miss 1 Group 28 pm_pteg8
PM_INST_PTEG_FROM_RMEM_GRP28 Instruction PTEG loaded from remote memory 2 Group 28 pm_pteg8
PM_INST_PTEG_FROM_L2MISS_GRP28 Instruction PTEG loaded from L2 miss 3 Group 28 pm_pteg8
PM_RUN_INST_CMPL_GRP28 Number of run instructions completed. 4 Group 28 pm_pteg8
PM_RUN_CYC_GRP28 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 28 pm_pteg8
PM_PTEG_FROM_L2_GRP29 A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store. 0 Group 29 pm_pteg9
PM_PTEG_FROM_L3_GRP29 A Page Table Entry was loaded into the TLB from the local L3 due to a demand load. 1 Group 29 pm_pteg9
PM_PTEG_FROM_RMEM_GRP29 A Page Table Entry was loaded into the TLB from memory attached to a different module than this processor is located on. 2 Group 29 pm_pteg9
PM_PTEG_FROM_L2MISS_GRP29 A Page Table Entry was loaded into the TLB but not from the local L2. 3 Group 29 pm_pteg9
PM_RUN_INST_CMPL_GRP29 Number of run instructions completed. 4 Group 29 pm_pteg9
PM_RUN_CYC_GRP29 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 29 pm_pteg9
PM_PTEG_FROM_L2_GRP30 A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store. 0 Group 30 pm_pteg10
PM_PTEG_FROM_L3_GRP30 A Page Table Entry was loaded into the TLB from the local L3 due to a demand load. 1 Group 30 pm_pteg10
PM_INST_CMPL_GRP30 Number of PowerPC Instructions that completed. 2 Group 30 pm_pteg10
PM_CYC_GRP30 Processor Cycles 3 Group 30 pm_pteg10
PM_RUN_INST_CMPL_GRP30 Number of run instructions completed. 4 Group 30 pm_pteg10
PM_RUN_CYC_GRP30 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 30 pm_pteg10
PM_PTEG_FROM_RL2L3_MOD_GRP31 A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store. 0 Group 31 pm_pteg11
PM_PTEG_FROM_RL2L3_SHR_GRP31 A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store. 1 Group 31 pm_pteg11
PM_INST_CMPL_GRP31 Number of PowerPC Instructions that completed. 2 Group 31 pm_pteg11
PM_PTEG_FROM_DL2L3_MOD_GRP31 A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store. 3 Group 31 pm_pteg11
PM_RUN_INST_CMPL_GRP31 Number of run instructions completed. 4 Group 31 pm_pteg11
PM_RUN_CYC_GRP31 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 31 pm_pteg11
PM_INST_CMPL_GRP32 Number of PowerPC Instructions that completed. 0 Group 32 pm_pteg12
PM_PTEG_FROM_DMEM_GRP32 A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store. 1 Group 32 pm_pteg12
PM_PTEG_FROM_RMEM_GRP32 A Page Table Entry was loaded into the TLB from memory attached to a different module than this processor is located on. 2 Group 32 pm_pteg12
PM_PTEG_FROM_LMEM_GRP32 A Page Table Entry was loaded into the TLB from memory attached to the same module this processor is located on. 3 Group 32 pm_pteg12
PM_RUN_INST_CMPL_GRP32 Number of run instructions completed. 4 Group 32 pm_pteg12
PM_RUN_CYC_GRP32 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 32 pm_pteg12
PM_POWER_EVENT1_GRP33 Power Management Event 1 0 Group 33 pm_freq1
PM_DPU_HELD_POWER_GRP33 Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time 1 Group 33 pm_freq1
PM_FREQ_DOWN_GRP33 Processor frequency was slowed down due to power management 2 Group 33 pm_freq1
PM_FREQ_UP_GRP33 Processor frequency was sped up due to power management 3 Group 33 pm_freq1
PM_RUN_INST_CMPL_GRP33 Number of run instructions completed. 4 Group 33 pm_freq1
PM_RUN_CYC_GRP33 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 33 pm_freq1
PM_POWER_EVENT1_GRP34 Power Management Event 1 0 Group 34 pm_freq2
PM_DPU_HELD_POWER_GRP34 Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time 1 Group 34 pm_freq2
PM_DISP_HELD_THERMAL_GRP34 Dispatch Held due to Thermal 2 Group 34 pm_freq2
PM_FREQ_UP_GRP34 Processor frequency was sped up due to power management 3 Group 34 pm_freq2
PM_RUN_INST_CMPL_GRP34 Number of run instructions completed. 4 Group 34 pm_freq2
PM_RUN_CYC_GRP34 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 34 pm_freq2
PM_LD_REF_L1_GRP35 L1 D cache load references counted at finish 0 Group 35 pm_L1_ref
PM_LD_REF_L1_LSU0_GRP35 Load references to Level 1 Data Cache, by unit 0. 1 Group 35 pm_L1_ref
PM_LD_REF_L1_LSU1_GRP35 Load references to Level 1 Data Cache, by unit 1. 2 Group 35 pm_L1_ref
PM_LSU_TWO_TABLEWALK_CYC_GRP35 Cycles when two tablewalks pending on this thread 3 Group 35 pm_L1_ref
PM_RUN_INST_CMPL_GRP35 Number of run instructions completed. 4 Group 35 pm_L1_ref
PM_RUN_CYC_GRP35 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 35 pm_L1_ref
PM_FLUSH_DISP_SYNC_GRP36 Dispatch Flush: Sync 0 Group 36 pm_flush1
PM_FLUSH_DISP_TLBIE_GRP36 Dispatch Flush: TLBIE 1 Group 36 pm_flush1
PM_FLUSH_DISP_SB_GRP36 Dispatch Flush: Scoreboard 2 Group 36 pm_flush1
PM_FLUSH_GRP36 Flushes occurred including LSU and Branch flushes. 3 Group 36 pm_flush1
PM_RUN_INST_CMPL_GRP36 Number of run instructions completed. 4 Group 36 pm_flush1
PM_RUN_CYC_GRP36 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 36 pm_flush1
PM_FLUSH_PARTIAL_GRP37 Partial flush 0 Group 37 pm_flush2
PM_FLUSH_DISP_GRP37 Dispatch flush 1 Group 37 pm_flush2
PM_LSU_FLUSH_GRP37 A flush was initiated by the Load Store Unit. 2 Group 37 pm_flush2
PM_LSU_PARTIAL_CDF_GRP37 A partial cacheline was returned from the L3 3 Group 37 pm_flush2
PM_RUN_INST_CMPL_GRP37 Number of run instructions completed. 4 Group 37 pm_flush2
PM_RUN_CYC_GRP37 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 37 pm_flush2
PM_FLUSH_DISP_GRP38 Dispatch flush 0 Group 38 pm_flush
PM_CYC_GRP38 Processor Cycles 1 Group 38 pm_flush
PM_FLUSH_COMPLETION_GRP38 Completion Flush 2 Group 38 pm_flush
PM_FLUSH_GRP38 Flushes occurred including LSU and Branch flushes. 3 Group 38 pm_flush
PM_RUN_INST_CMPL_GRP38 Number of run instructions completed. 4 Group 38 pm_flush
PM_RUN_CYC_GRP38 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 38 pm_flush
PM_LSU_FLUSH_ULD_GRP39 A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1. 0 Group 39 pm_lsu_flush1
PM_LSU_FLUSH_UST_GRP39 A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1. 1 Group 39 pm_lsu_flush1
PM_LSU_FLUSH_LRQ_GRP39 Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1. 2 Group 39 pm_lsu_flush1
PM_LSU_FLUSH_SRQ_GRP39 Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1. 3 Group 39 pm_lsu_flush1
PM_RUN_INST_CMPL_GRP39 Number of run instructions completed. 4 Group 39 pm_lsu_flush1
PM_RUN_CYC_GRP39 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 39 pm_lsu_flush1
PM_LSU_FLUSH_ULD_GRP40 A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1. 0 Group 40 pm_lsu_flush2
PM_LSU0_FLUSH_ULD_GRP40 A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1) 1 Group 40 pm_lsu_flush2
PM_LSU1_FLUSH_ULD_GRP40 A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1). 2 Group 40 pm_lsu_flush2
PM_FLUSH_GRP40 Flushes occurred including LSU and Branch flushes. 3 Group 40 pm_lsu_flush2
PM_RUN_INST_CMPL_GRP40 Number of run instructions completed. 4 Group 40 pm_lsu_flush2
PM_RUN_CYC_GRP40 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 40 pm_lsu_flush2
PM_LSU_FLUSH_UST_GRP41 A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1. 0 Group 41 pm_lsu_flush3
PM_LSU0_FLUSH_UST_GRP41 A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary). 1 Group 41 pm_lsu_flush3
PM_LSU1_FLUSH_UST_GRP41 A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary) 2 Group 41 pm_lsu_flush3
PM_FLUSH_GRP41 Flushes occurred including LSU and Branch flushes. 3 Group 41 pm_lsu_flush3
PM_RUN_INST_CMPL_GRP41 Number of run instructions completed. 4 Group 41 pm_lsu_flush3
PM_RUN_CYC_GRP41 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 41 pm_lsu_flush3
PM_LSU_FLUSH_LRQ_GRP42 Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1. 0 Group 42 pm_lsu_flush4
PM_LSU0_FLUSH_LRQ_GRP42 Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. 1 Group 42 pm_lsu_flush4
PM_LSU1_FLUSH_LRQ_GRP42 Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. 2 Group 42 pm_lsu_flush4
PM_FLUSH_GRP42 Flushes occurred including LSU and Branch flushes. 3 Group 42 pm_lsu_flush4
PM_RUN_INST_CMPL_GRP42 Number of run instructions completed. 4 Group 42 pm_lsu_flush4
PM_RUN_CYC_GRP42 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 42 pm_lsu_flush4
PM_LSU_FLUSH_SRQ_GRP43 Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1. 0 Group 43 pm_lsu_flush5
PM_LSU0_FLUSH_SRQ_GRP43 Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. 1 Group 43 pm_lsu_flush5
PM_LSU1_FLUSH_SRQ_GRP43 Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. 2 Group 43 pm_lsu_flush5
PM_FLUSH_GRP43 Flushes occurred including LSU and Branch flushes. 3 Group 43 pm_lsu_flush5
PM_RUN_INST_CMPL_GRP43 Number of run instructions completed. 4 Group 43 pm_lsu_flush5
PM_RUN_CYC_GRP43 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 43 pm_lsu_flush5
PM_IC_DEMAND_CYC_GRP44 Cycles when a demand ifetch was pending 0 Group 44 pm_prefetch
PM_IC_PREF_REQ_GRP44 An instruction prefetch request has been made. 1 Group 44 pm_prefetch
PM_IC_RELOAD_SHR_GRP44 An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads. 2 Group 44 pm_prefetch
PM_IC_PREF_WRITE_GRP44 Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch. 3 Group 44 pm_prefetch
PM_RUN_INST_CMPL_GRP44 Number of run instructions completed. 4 Group 44 pm_prefetch
PM_RUN_CYC_GRP44 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 44 pm_prefetch
PM_ANY_THRD_RUN_CYC_GRP45 One of threads in run_cycles 0 Group 45 pm_thread_cyc1
PM_THRD_ALL_RUN_CYC_GRP45 Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. 1 Group 45 pm_thread_cyc1
PM_THRD_CONC_RUN_INST_GRP45 Instructions completed by this thread when both threads had their run latches set. 2 Group 45 pm_thread_cyc1
PM_THRD_4_RUN_CYC_GRP45 4 thread in Run Cycles 3 Group 45 pm_thread_cyc1
PM_RUN_INST_CMPL_GRP45 Number of run instructions completed. 4 Group 45 pm_thread_cyc1
PM_RUN_CYC_GRP45 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 45 pm_thread_cyc1
PM_THRD_GRP_CMPL_BOTH_CYC_GRP46 Cycles that both threads completed. 0 Group 46 pm_thread_cyc2
PM_THRD_ALL_RUN_CYC_GRP46 Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. 1 Group 46 pm_thread_cyc2
PM_THRD_CONC_RUN_INST_GRP46 Instructions completed by this thread when both threads had their run latches set. 2 Group 46 pm_thread_cyc2
PM_THRD_PRIO_0_1_CYC_GRP46 Cycles thread running at priority level 0 or 1 3 Group 46 pm_thread_cyc2
PM_RUN_INST_CMPL_GRP46 Number of run instructions completed. 4 Group 46 pm_thread_cyc2
PM_RUN_CYC_GRP46 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 46 pm_thread_cyc2
PM_THRD_3_CONC_RUN_INST_GRP47 3 thread Concurrent Run Instructions 0 Group 47 pm_thread_cyc3
PM_THRD_2_RUN_CYC_GRP47 2 thread in Run Cycles 1 Group 47 pm_thread_cyc3
PM_THRD_3_RUN_CYC_GRP47 3 thread in Run Cycles 2 Group 47 pm_thread_cyc3
PM_THRD_PRIO_4_5_CYC_GRP47 Cycles thread running at priority level 4 or 5 3 Group 47 pm_thread_cyc3
PM_RUN_INST_CMPL_GRP47 Number of run instructions completed. 4 Group 47 pm_thread_cyc3
PM_RUN_CYC_GRP47 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 47 pm_thread_cyc3
PM_THRD_PRIO_2_3_CYC_GRP48 Cycles thread running at priority level 2 or 3 0 Group 48 pm_thread_cyc4
PM_THRD_4_CONC_RUN_INST_GRP48 4 thread Concurrent Run Instructions 1 Group 48 pm_thread_cyc4
PM_1THRD_CON_RUN_INSTR_GRP48 1 thread Concurrent Run Instructions 2 Group 48 pm_thread_cyc4
PM_THRD_2_CONC_RUN_INSTR_GRP48 2 thread Concurrent Run Instructions 3 Group 48 pm_thread_cyc4
PM_RUN_INST_CMPL_GRP48 Number of run instructions completed. 4 Group 48 pm_thread_cyc4
PM_RUN_CYC_GRP48 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 48 pm_thread_cyc4
PM_THRD_PRIO_0_1_CYC_GRP49 Cycles thread running at priority level 0 or 1 0 Group 49 pm_thread_cyc5
PM_THRD_PRIO_2_3_CYC_GRP49 Cycles thread running at priority level 2 or 3 1 Group 49 pm_thread_cyc5
PM_THRD_PRIO_4_5_CYC_GRP49 Cycles thread running at priority level 4 or 5 2 Group 49 pm_thread_cyc5
PM_THRD_PRIO_6_7_CYC_GRP49 Cycles thread running at priority level 6 or 7 3 Group 49 pm_thread_cyc5
PM_RUN_INST_CMPL_GRP49 Number of run instructions completed. 4 Group 49 pm_thread_cyc5
PM_RUN_CYC_GRP49 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 49 pm_thread_cyc5
PM_THRD_1_RUN_CYC_GRP50 At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT. 0 Group 50 pm_thread_cyc6
PM_THRD_ALL_RUN_CYC_GRP50 Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. 1 Group 50 pm_thread_cyc6
PM_THRD_CONC_RUN_INST_GRP50 Instructions completed by this thread when both threads had their run latches set. 2 Group 50 pm_thread_cyc6
PM_THRD_4_RUN_CYC_GRP50 4 thread in Run Cycles 3 Group 50 pm_thread_cyc6
PM_RUN_INST_CMPL_GRP50 Number of run instructions completed. 4 Group 50 pm_thread_cyc6
PM_RUN_CYC_GRP50 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 50 pm_thread_cyc6
PM_FXU_IDLE_GRP51 FXU0 and FXU1 are both idle. 0 Group 51 pm_fxu1
PM_FXU_BUSY_GRP51 Cycles when both FXU0 and FXU1 are busy. 1 Group 51 pm_fxu1
PM_FXU0_BUSY_FXU1_IDLE_GRP51 FXU0 is busy while FXU1 was idle 2 Group 51 pm_fxu1
PM_FXU1_BUSY_FXU0_IDLE_GRP51 FXU0 was idle while FXU1 was busy 3 Group 51 pm_fxu1
PM_RUN_INST_CMPL_GRP51 Number of run instructions completed. 4 Group 51 pm_fxu1
PM_RUN_CYC_GRP51 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 51 pm_fxu1
PM_FXU0_FIN_GRP52 The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete. 0 Group 52 pm_fxu2
PM_RUN_CYC_GRP52 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 52 pm_fxu2
PM_INST_CMPL_GRP52 Number of PowerPC Instructions that completed. 2 Group 52 pm_fxu2
PM_FXU1_FIN_GRP52 The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete. 3 Group 52 pm_fxu2
PM_RUN_INST_CMPL_GRP52 Number of run instructions completed. 4 Group 52 pm_fxu2
PM_RUN_CYC_GRP52 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 52 pm_fxu2
PM_CYC_GRP53 Processor Cycles 0 Group 53 pm_fxu3
PM_FXU_BUSY_GRP53 Cycles when both FXU0 and FXU1 are busy. 1 Group 53 pm_fxu3
PM_FXU0_BUSY_FXU1_IDLE_GRP53 FXU0 is busy while FXU1 was idle 2 Group 53 pm_fxu3
PM_FXU1_BUSY_FXU0_IDLE_GRP53 FXU0 was idle while FXU1 was busy 3 Group 53 pm_fxu3
PM_RUN_INST_CMPL_GRP53 Number of run instructions completed. 4 Group 53 pm_fxu3
PM_RUN_CYC_GRP53 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 53 pm_fxu3
PM_FXU_IDLE_GRP54 FXU0 and FXU1 are both idle. 0 Group 54 pm_fxu4
PM_FXU_BUSY_GRP54 Cycles when both FXU0 and FXU1 are busy. 1 Group 54 pm_fxu4
PM_CYC_GRP54 Processor Cycles 2 Group 54 pm_fxu4
PM_INST_CMPL_GRP54 Number of PowerPC Instructions that completed. 3 Group 54 pm_fxu4
PM_RUN_INST_CMPL_GRP54 Number of run instructions completed. 4 Group 54 pm_fxu4
PM_RUN_CYC_GRP54 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 54 pm_fxu4
PM_L2_RCLD_DISP_GRP55 L2 RC load dispatch attempt 0 Group 55 pm_L2_RCLD
PM_L2_RCLD_DISP_FAIL_OTHER_GRP55 L2 RC load dispatch attempt failed due to other reasons 1 Group 55 pm_L2_RCLD
PM_L2_RCST_DISP_GRP55 L2 RC store dispatch attempt 2 Group 55 pm_L2_RCLD
PM_L2_RCLD_BUSY_RC_FULL_GRP55 L2 activated Busy to the core for loads due to all RC full 3 Group 55 pm_L2_RCLD
PM_RUN_INST_CMPL_GRP55 Number of run instructions completed. 4 Group 55 pm_L2_RCLD
PM_RUN_CYC_GRP55 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 55 pm_L2_RCLD
PM_L2_CO_FAIL_BUSY_GRP56 L2 RC Cast Out dispatch attempt failed due to all CO machines busy 0 Group 56 pm_L2_RC
PM_CYC_GRP56 Processor Cycles 1 Group 56 pm_L2_RC
PM_L2_RC_ST_DONE_GRP56 RC did st to line that was Tx or Sx 2 Group 56 pm_L2_RC
PM_INST_CMPL_GRP56 Number of PowerPC Instructions that completed. 3 Group 56 pm_L2_RC
PM_RUN_INST_CMPL_GRP56 Number of run instructions completed. 4 Group 56 pm_L2_RC
PM_RUN_CYC_GRP56 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 56 pm_L2_RC
PM_L2_RCLD_DISP_GRP57 L2 RC load dispatch attempt 0 Group 57 pm_L2_RCST
PM_L2_RCLD_DISP_FAIL_OTHER_GRP57 L2 RC load dispatch attempt failed due to other reasons 1 Group 57 pm_L2_RCST
PM_L2_RCST_DISP_FAIL_ADDR_GRP57 L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ 2 Group 57 pm_L2_RCST
PM_L2_RCST_DISP_FAIL_OTHER_GRP57 L2 RC store dispatch attempt failed due to other reasons 3 Group 57 pm_L2_RCST
PM_RUN_INST_CMPL_GRP57 Number of run instructions completed. 4 Group 57 pm_L2_RCST
PM_RUN_CYC_GRP57 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 57 pm_L2_RCST
PM_L2_ST_GRP58 Data Store Count 0 Group 58 pm_L2_ldst_1
PM_L2_LD_MISS_GRP58 Data Load Miss 1 Group 58 pm_L2_ldst_1
PM_INST_CMPL_GRP58 Number of PowerPC Instructions that completed. 2 Group 58 pm_L2_ldst_1
PM_CYC_GRP58 Processor Cycles 3 Group 58 pm_L2_ldst_1
PM_RUN_INST_CMPL_GRP58 Number of run instructions completed. 4 Group 58 pm_L2_ldst_1
PM_RUN_CYC_GRP58 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 58 pm_L2_ldst_1
PM_INST_CMPL_GRP59 Number of PowerPC Instructions that completed. 0 Group 59 pm_L2_ldst_2
PM_CYC_GRP59 Processor Cycles 1 Group 59 pm_L2_ldst_2
PM_L2_LD_HIT_GRP59 A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Total for all slices 2 Group 59 pm_L2_ldst_2
PM_L2_ST_HIT_GRP59 A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Total for all slices. 3 Group 59 pm_L2_ldst_2
PM_RUN_INST_CMPL_GRP59 Number of run instructions completed. 4 Group 59 pm_L2_ldst_2
PM_RUN_CYC_GRP59 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 59 pm_L2_ldst_2
PM_INST_CMPL_GRP60 Number of PowerPC Instructions that completed. 0 Group 60 pm_L2_ldst_3
PM_CYC_GRP60 Processor Cycles 1 Group 60 pm_L2_ldst_3
PM_L2_LD_DISP_GRP60 All successful load dispatches 2 Group 60 pm_L2_ldst_3
PM_L2_ST_DISP_GRP60 All successful store dispatches 3 Group 60 pm_L2_ldst_3
PM_RUN_INST_CMPL_GRP60 Number of run instructions completed. 4 Group 60 pm_L2_ldst_3
PM_RUN_CYC_GRP60 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 60 pm_L2_ldst_3
PM_L2_RCLD_DISP_FAIL_ADDR_GRP61 L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ 0 Group 61 pm_L2_RCSTLD
PM_L2_RCST_BUSY_RC_FULL_GRP61 L2 activated Busy to the core for stores due to all RC full 1 Group 61 pm_L2_RCSTLD
PM_INST_CMPL_GRP61 Number of PowerPC Instructions that completed. 2 Group 61 pm_L2_RCSTLD
PM_CYC_GRP61 Processor Cycles 3 Group 61 pm_L2_RCSTLD
PM_RUN_INST_CMPL_GRP61 Number of run instructions completed. 4 Group 61 pm_L2_RCSTLD
PM_RUN_CYC_GRP61 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 61 pm_L2_RCSTLD
PM_PB_NODE_PUMP_GRP62 Nest events (MC0/MC1/PB/GX), Pair0 Bit0 0 Group 62 pm_nest1
PM_PB_SYS_PUMP_GRP62 Nest events (MC0/MC1/PB/GX), Pair1 Bit0 1 Group 62 pm_nest1
PM_PB_RETRY_NODE_PUMP_GRP62 Nest events (MC0/MC1/PB/GX), Pair2 Bit0 2 Group 62 pm_nest1
PM_PB_RETRY_SYS_PUMP_GRP62 Nest events (MC0/MC1/PB/GX), Pair3 Bit0 3 Group 62 pm_nest1
PM_RUN_INST_CMPL_GRP62 Number of run instructions completed. 4 Group 62 pm_nest1
PM_RUN_CYC_GRP62 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 62 pm_nest1
PM_MEM0_RQ_DISP_GRP63 Nest events (MC0/MC1/PB/GX), Pair0 Bit1 0 Group 63 pm_nest2
PM_MEM0_PREFETCH_DISP_GRP63 Nest events (MC0/MC1/PB/GX), Pair1 Bit1 1 Group 63 pm_nest2
PM_MEM0_PB_RD_CL_GRP63 Nest events (MC0/MC1/PB/GX), Pair2 Bit1 2 Group 63 pm_nest2
PM_MEM0_WQ_DISP_GRP63 Nest events (MC0/MC1/PB/GX), Pair3 Bit1 3 Group 63 pm_nest2
PM_RUN_INST_CMPL_GRP63 Number of run instructions completed. 4 Group 63 pm_nest2
PM_RUN_CYC_GRP63 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 63 pm_nest2
PM_NEST_PAIR0_ADD_GRP64 Nest events (MC0/MC1/PB/GX), Pair0 ADD 0 Group 64 pm_nest3
PM_NEST_PAIR1_ADD_GRP64 Nest events (MC0/MC1/PB/GX), Pair1 ADD 1 Group 64 pm_nest3
PM_NEST_PAIR2_ADD_GRP64 Nest events (MC0/MC1/PB/GX), Pair2 ADD 2 Group 64 pm_nest3
PM_NEST_PAIR3_ADD_GRP64 Nest events (MC0/MC1/PB/GX), Pair3 ADD 3 Group 64 pm_nest3
PM_RUN_INST_CMPL_GRP64 Number of run instructions completed. 4 Group 64 pm_nest3
PM_RUN_CYC_GRP64 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 64 pm_nest3
PM_NEST_PAIR0_AND_GRP65 Nest events (MC0/MC1/PB/GX), Pair0 AND 0 Group 65 pm_nest4
PM_NEST_PAIR1_AND_GRP65 Nest events (MC0/MC1/PB/GX), Pair1 AND 1 Group 65 pm_nest4
PM_NEST_PAIR2_AND_GRP65 Nest events (MC0/MC1/PB/GX), Pair2 AND 2 Group 65 pm_nest4
PM_NEST_PAIR3_AND_GRP65 Nest events (MC0/MC1/PB/GX), Pair3 AND 3 Group 65 pm_nest4
PM_RUN_INST_CMPL_GRP65 Number of run instructions completed. 4 Group 65 pm_nest4
PM_RUN_CYC_GRP65 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 65 pm_nest4
PM_IC_DEMAND_L2_BHT_REDIRECT_GRP66 A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict). 0 Group 66 pm_L2_redir_pref
PM_IC_DEMAND_L2_BR_REDIRECT_GRP66 A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target). 1 Group 66 pm_L2_redir_pref
PM_IC_DEMAND_REQ_GRP66 Demand Instruction fetch request 2 Group 66 pm_L2_redir_pref
PM_IC_BANK_CONFLICT_GRP66 Read blocked due to interleave conflict. 3 Group 66 pm_L2_redir_pref
PM_RUN_INST_CMPL_GRP66 Number of run instructions completed. 4 Group 66 pm_L2_redir_pref
PM_RUN_CYC_GRP66 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 66 pm_L2_redir_pref
PM_DATA_FROM_L2_GRP67 The processor's Data Cache was reloaded from the local L2 due to a demand load. 0 Group 67 pm_dlatencies1
PM_INST_DISP_GRP67 Number of PowerPC instructions successfully dispatched. 1 Group 67 pm_dlatencies1
PM_L1_DCACHE_RELOAD_VALID_GRP67 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 67 pm_dlatencies1
PM_1PLUS_PPC_DISP_GRP67 A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. 3 Group 67 pm_dlatencies1
PM_RUN_INST_CMPL_GRP67 Number of run instructions completed. 4 Group 67 pm_dlatencies1
PM_RUN_CYC_GRP67 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 67 pm_dlatencies1
PM_DATA_FROM_L3_GRP68 The processor's Data Cache was reloaded from the local L3 due to a demand load. 0 Group 68 pm_dlatencies2
PM_CYC_GRP68 Processor Cycles 1 Group 68 pm_dlatencies2
PM_L1_DCACHE_RELOAD_VALID_GRP68 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 68 pm_dlatencies2
PM_INST_CMPL_GRP68 Number of PowerPC Instructions that completed. 3 Group 68 pm_dlatencies2
PM_RUN_INST_CMPL_GRP68 Number of run instructions completed. 4 Group 68 pm_dlatencies2
PM_RUN_CYC_GRP68 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 68 pm_dlatencies2
PM_DATA_FROM_RL2L3_MOD_GRP69 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load 0 Group 69 pm_dlatencies3
PM_DATA_FROM_RL2L3_SHR_GRP69 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load 1 Group 69 pm_dlatencies3
PM_L1_DCACHE_RELOAD_VALID_GRP69 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 69 pm_dlatencies3
PM_INST_CMPL_GRP69 Number of PowerPC Instructions that completed. 3 Group 69 pm_dlatencies3
PM_RUN_INST_CMPL_GRP69 Number of run instructions completed. 4 Group 69 pm_dlatencies3
PM_RUN_CYC_GRP69 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 69 pm_dlatencies3
PM_LSU_REJECT_GRP70 The Load Store Unit rejected an instruction. Combined Unit 0 + 1 0 Group 70 pm_rejects1
PM_LSU0_REJECT_LHS_GRP70 Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. 1 Group 70 pm_rejects1
PM_LSU1_REJECT_LHS_GRP70 Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. 2 Group 70 pm_rejects1
PM_LSU_REJECT_LHS_GRP70 The Load Store Unit rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1 3 Group 70 pm_rejects1
PM_RUN_INST_CMPL_GRP70 Number of run instructions completed. 4 Group 70 pm_rejects1
PM_RUN_CYC_GRP70 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 70 pm_rejects1
PM_LSU_REJECT_GRP71 The Load Store Unit rejected an instruction. Combined Unit 0 + 1 0 Group 71 pm_rejects2
PM_LSU_REJECT_ERAT_MISS_GRP71 Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat. 1 Group 71 pm_rejects2
PM_LSU_REJECT_SET_MPRED_GRP71 The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1 2 Group 71 pm_rejects2
PM_LSU_SRQ_EMPTY_CYC_GRP71 The Store Request Queue is empty 3 Group 71 pm_rejects2
PM_RUN_INST_CMPL_GRP71 Number of run instructions completed. 4 Group 71 pm_rejects2
PM_RUN_CYC_GRP71 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 71 pm_rejects2
PM_LSU_REJECT_SET_MPRED_GRP72 The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1 0 Group 72 pm_rejects3
PM_LSU_SET_MPRED_GRP72 Line already in cache at reload time 1 Group 72 pm_rejects3
PM_CYC_GRP72 Processor Cycles 2 Group 72 pm_rejects3
PM_INST_CMPL_GRP72 Number of PowerPC Instructions that completed. 3 Group 72 pm_rejects3
PM_RUN_INST_CMPL_GRP72 Number of run instructions completed. 4 Group 72 pm_rejects3
PM_RUN_CYC_GRP72 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 72 pm_rejects3
PM_LSU_REJECT_LMQ_FULL_GRP73 Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1. 0 Group 73 pm_lsu_reject
PM_LSU0_REJECT_LMQ_FULL_GRP73 Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. 1 Group 73 pm_lsu_reject
PM_LSU1_REJECT_LMQ_FULL_GRP73 Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. 2 Group 73 pm_lsu_reject
PM_INST_CMPL_GRP73 Number of PowerPC Instructions that completed. 3 Group 73 pm_lsu_reject
PM_RUN_INST_CMPL_GRP73 Number of run instructions completed. 4 Group 73 pm_lsu_reject
PM_RUN_CYC_GRP73 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 73 pm_lsu_reject
PM_LSU_NCLD_GRP74 A non-cacheable load was executed. Combined Unit 0 + 1. 0 Group 74 pm_lsu_ncld
PM_LSU0_NCLD_GRP74 A non-cacheable load was executed by unit 0. 1 Group 74 pm_lsu_ncld
PM_LSU1_NCLD_GRP74 A non-cacheable load was executed by Unit 0. 2 Group 74 pm_lsu_ncld
PM_INST_CMPL_GRP74 Number of PowerPC Instructions that completed. 3 Group 74 pm_lsu_ncld
PM_RUN_INST_CMPL_GRP74 Number of run instructions completed. 4 Group 74 pm_lsu_ncld
PM_RUN_CYC_GRP74 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 74 pm_lsu_ncld
PM_GCT_NOSLOT_CYC_GRP75 Cycles when the Global Completion Table has no slots from this thread. 0 Group 75 pm_gct1
PM_GCT_EMPTY_CYC_GRP75 Cycles when the Global Completion Table was completely empty. No thread had an entry allocated. 1 Group 75 pm_gct1
PM_GCT_FULL_CYC_GRP75 The Global Completion Table is completely full. 2 Group 75 pm_gct1
PM_CYC_GRP75 Processor Cycles 3 Group 75 pm_gct1
PM_RUN_INST_CMPL_GRP75 Number of run instructions completed. 4 Group 75 pm_gct1
PM_RUN_CYC_GRP75 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 75 pm_gct1
PM_GCT_UTIL_1_TO_2_SLOTS_GRP76 GCT Utilization 1-2 entries 0 Group 76 pm_gct2
PM_GCT_UTIL_3_TO_6_SLOTS_GRP76 GCT Utilization 3-6 entries 1 Group 76 pm_gct2
PM_GCT_UTIL_7_TO_10_SLOTS_GRP76 GCT Utilization 7-10 entries 2 Group 76 pm_gct2
PM_GCT_UTIL_11_PLUS_SLOTS_GRP76 GCT Utilization 11+ entries 3 Group 76 pm_gct2
PM_RUN_INST_CMPL_GRP76 Number of run instructions completed. 4 Group 76 pm_gct2
PM_RUN_CYC_GRP76 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 76 pm_gct2
PM_L2_CASTOUT_MOD_GRP77 An L2 line in the Modified state was castout. Total for all slices. 0 Group 77 pm_L2_castout_invalidate_1
PM_L2_DC_INV_GRP77 The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Total for all slices 1 Group 77 pm_L2_castout_invalidate_1
PM_INST_CMPL_GRP77 Number of PowerPC Instructions that completed. 2 Group 77 pm_L2_castout_invalidate_1
PM_CYC_GRP77 Processor Cycles 3 Group 77 pm_L2_castout_invalidate_1
PM_RUN_INST_CMPL_GRP77 Number of run instructions completed. 4 Group 77 pm_L2_castout_invalidate_1
PM_RUN_CYC_GRP77 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 77 pm_L2_castout_invalidate_1
PM_L2_CASTOUT_SHR_GRP78 An L2 line in the Shared state was castout. Total for all slices. 0 Group 78 pm_L2_castout_invalidate_2
PM_L2_IC_INV_GRP78 Icache Invalidates from L2 1 Group 78 pm_L2_castout_invalidate_2
PM_INST_CMPL_GRP78 Number of PowerPC Instructions that completed. 2 Group 78 pm_L2_castout_invalidate_2
PM_CYC_GRP78 Processor Cycles 3 Group 78 pm_L2_castout_invalidate_2
PM_RUN_INST_CMPL_GRP78 Number of run instructions completed. 4 Group 78 pm_L2_castout_invalidate_2
PM_RUN_CYC_GRP78 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 78 pm_L2_castout_invalidate_2
PM_DISP_HELD_GRP79 Dispatch Held 0 Group 79 pm_disp_held1
PM_DPU_HELD_POWER_GRP79 Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time 1 Group 79 pm_disp_held1
PM_DISP_HELD_THERMAL_GRP79 Dispatch Held due to Thermal 2 Group 79 pm_disp_held1
PM_1PLUS_PPC_DISP_GRP79 A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. 3 Group 79 pm_disp_held1
PM_RUN_INST_CMPL_GRP79 Number of run instructions completed. 4 Group 79 pm_disp_held1
PM_RUN_CYC_GRP79 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 79 pm_disp_held1
PM_THERMAL_WARN_GRP80 Processor in Thermal Warning 0 Group 80 pm_disp_held2
PM_DPU_HELD_POWER_GRP80 Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time 1 Group 80 pm_disp_held2
PM_DISP_HELD_THERMAL_GRP80 Dispatch Held due to Thermal 2 Group 80 pm_disp_held2
PM_THERMAL_MAX_GRP80 The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software. 3 Group 80 pm_disp_held2
PM_RUN_INST_CMPL_GRP80 Number of run instructions completed. 4 Group 80 pm_disp_held2
PM_RUN_CYC_GRP80 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 80 pm_disp_held2
PM_DISP_CLB_HELD_BAL_GRP81 Dispatch/CLB Hold: Balance 0 Group 81 pm_disp_clb_held
PM_DISP_CLB_HELD_RES_GRP81 Dispatch/CLB Hold: Resource 1 Group 81 pm_disp_clb_held
PM_DISP_CLB_HELD_TLBIE_GRP81 Dispatch Hold: Due to TLBIE 2 Group 81 pm_disp_clb_held
PM_DISP_CLB_HELD_SYNC_GRP81 Dispatch/CLB Hold: Sync type instruction 3 Group 81 pm_disp_clb_held
PM_RUN_INST_CMPL_GRP81 Number of run instructions completed. 4 Group 81 pm_disp_clb_held
PM_RUN_CYC_GRP81 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 81 pm_disp_clb_held
PM_POWER_EVENT1_GRP82 Power Management Event 1 0 Group 82 pm_power
PM_POWER_EVENT2_GRP82 Power Management Event 2 1 Group 82 pm_power
PM_POWER_EVENT3_GRP82 Power Management Event 3 2 Group 82 pm_power
PM_POWER_EVENT4_GRP82 Power Management Event 4 3 Group 82 pm_power
PM_RUN_INST_CMPL_GRP82 Number of run instructions completed. 4 Group 82 pm_power
PM_RUN_CYC_GRP82 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 82 pm_power
PM_1PLUS_PPC_CMPL_GRP83 A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. 0 Group 83 pm_dispatch1
PM_INST_DISP_GRP83 Number of PowerPC instructions successfully dispatched. 1 Group 83 pm_dispatch1
PM_GRP_DISP_GRP83 A group was dispatched 2 Group 83 pm_dispatch1
PM_1PLUS_PPC_DISP_GRP83 A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. 3 Group 83 pm_dispatch1
PM_RUN_INST_CMPL_GRP83 Number of run instructions completed. 4 Group 83 pm_dispatch1
PM_RUN_CYC_GRP83 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 83 pm_dispatch1
PM_1PLUS_PPC_CMPL_GRP84 A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. 0 Group 84 pm_dispatch2
PM_CYC_GRP84 Processor Cycles 1 Group 84 pm_dispatch2
PM_INST_CMPL_GRP84 Number of PowerPC Instructions that completed. 2 Group 84 pm_dispatch2
PM_1PLUS_PPC_DISP_GRP84 A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. 3 Group 84 pm_dispatch2
PM_RUN_INST_CMPL_GRP84 Number of run instructions completed. 4 Group 84 pm_dispatch2
PM_RUN_CYC_GRP84 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 84 pm_dispatch2
PM_IC_REQ_ALL_GRP85 Icache requests, prefetch + demand 0 Group 85 pm_ic
PM_IC_WRITE_ALL_GRP85 Icache sectors written, prefetch + demand 1 Group 85 pm_ic
PM_IC_PREF_CANCEL_ALL_GRP85 Prefetch Canceled due to page boundary or icache hit 2 Group 85 pm_ic
PM_IC_DEMAND_L2_BR_ALL_GRP85 L2 I cache demand request due to BHT or redirect 3 Group 85 pm_ic
PM_RUN_INST_CMPL_GRP85 Number of run instructions completed. 4 Group 85 pm_ic
PM_RUN_CYC_GRP85 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 85 pm_ic
PM_IC_PREF_CANCEL_PAGE_GRP86 Prefetch Canceled due to page boundary 0 Group 86 pm_ic_pref_cancel
PM_IC_PREF_CANCEL_HIT_GRP86 Prefetch Canceled due to icache hit 1 Group 86 pm_ic_pref_cancel
PM_IC_PREF_CANCEL_L2_GRP86 L2 Squashed request 2 Group 86 pm_ic_pref_cancel
PM_IC_PREF_CANCEL_ALL_GRP86 Prefetch Canceled due to page boundary or icache hit 3 Group 86 pm_ic_pref_cancel
PM_RUN_INST_CMPL_GRP86 Number of run instructions completed. 4 Group 86 pm_ic_pref_cancel
PM_RUN_CYC_GRP86 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 86 pm_ic_pref_cancel
PM_IERAT_MISS_GRP87 A translation request missed the Instruction Effective to Real Address Translation (ERAT) table 0 Group 87 pm_ic_miss
PM_L1_ICACHE_MISS_GRP87 An instruction fetch request missed the L1 cache. 1 Group 87 pm_ic_miss
PM_INST_CMPL_GRP87 Number of PowerPC Instructions that completed. 2 Group 87 pm_ic_miss
PM_CYC_GRP87 Processor Cycles 3 Group 87 pm_ic_miss
PM_RUN_INST_CMPL_GRP87 Number of run instructions completed. 4 Group 87 pm_ic_miss
PM_RUN_CYC_GRP87 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 87 pm_ic_miss
PM_DATA_FROM_L2_GRP88 The processor's Data Cache was reloaded from the local L2 due to a demand load. 0 Group 88 pm_cpi_stack1
PM_CMPLU_STALL_DCACHE_MISS_GRP88 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU. 1 Group 88 pm_cpi_stack1
PM_L1_DCACHE_RELOAD_VALID_GRP88 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 88 pm_cpi_stack1
PM_CMPLU_STALL_ERAT_MISS_GRP88 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT. 3 Group 88 pm_cpi_stack1
PM_RUN_INST_CMPL_GRP88 Number of run instructions completed. 4 Group 88 pm_cpi_stack1
PM_RUN_CYC_GRP88 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 88 pm_cpi_stack1
PM_FXU_IDLE_GRP89 FXU0 and FXU1 are both idle. 0 Group 89 pm_cpi_stack2
PM_CMPLU_STALL_FXU_GRP89 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction. 1 Group 89 pm_cpi_stack2
PM_GRP_CMPL_GRP89 A group completed. Microcoded instructions that span multiple groups will generate this event once per group. 2 Group 89 pm_cpi_stack2
PM_CMPLU_STALL_DIV_GRP89 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU. 3 Group 89 pm_cpi_stack2
PM_RUN_INST_CMPL_GRP89 Number of run instructions completed. 4 Group 89 pm_cpi_stack2
PM_RUN_CYC_GRP89 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 89 pm_cpi_stack2
PM_TABLEWALK_CYC_GRP90 Cycles doing instruction or data tablewalks 0 Group 90 pm_cpi_stack3
PM_CMPLU_STALL_LSU_GRP90 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction. 1 Group 90 pm_cpi_stack3
PM_DATA_TABLEWALK_CYC_GRP90 Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried. 2 Group 90 pm_cpi_stack3
PM_CMPLU_STALL_REJECT_GRP90 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU. 3 Group 90 pm_cpi_stack3
PM_RUN_INST_CMPL_GRP90 Number of run instructions completed. 4 Group 90 pm_cpi_stack3
PM_RUN_CYC_GRP90 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 90 pm_cpi_stack3
PM_FLOP_GRP91 A floating point operation has completed 0 Group 91 pm_cpi_stack4
PM_CMPLU_STALL_SCALAR_LONG_GRP91 Completion stall caused by long latency scalar instruction 1 Group 91 pm_cpi_stack4
PM_MRK_STALL_CMPLU_CYC_GRP91 Marked Group Completion Stall cycles 2 Group 91 pm_cpi_stack4
PM_CMPLU_STALL_SCALAR_GRP91 Completion stall caused by FPU instruction 3 Group 91 pm_cpi_stack4
PM_RUN_INST_CMPL_GRP91 Number of run instructions completed. 4 Group 91 pm_cpi_stack4
PM_RUN_CYC_GRP91 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 91 pm_cpi_stack4
PM_CMPLU_STALL_END_GCT_NOSLOT_GRP92 Count ended because GCT went empty 0 Group 92 pm_cpi_stack5
PM_CMPLU_STALL_VECTOR_GRP92 Completion stall caused by Vector instruction 1 Group 92 pm_cpi_stack5
PM_MRK_STALL_CMPLU_CYC_COUNT_GRP92 Marked Group Completion Stall cycles (use edge detect to count #) 2 Group 92 pm_cpi_stack5
PM_CMPLU_STALL_GRP92 No groups completed, GCT not empty 3 Group 92 pm_cpi_stack5
PM_RUN_INST_CMPL_GRP92 Number of run instructions completed. 4 Group 92 pm_cpi_stack5
PM_RUN_CYC_GRP92 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 92 pm_cpi_stack5
PM_CMPLU_STALL_THRD_GRP93 Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn 0 Group 93 pm_cpi_stack6
PM_CMPLU_STALL_DFU_GRP93 Completion stall caused by Decimal Floating Point Unit 1 Group 93 pm_cpi_stack6
PM_INST_CMPL_GRP93 Number of PowerPC Instructions that completed. 2 Group 93 pm_cpi_stack6
PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP93 No slot in GCT caused by branch mispredict or I cache miss 3 Group 93 pm_cpi_stack6
PM_RUN_INST_CMPL_GRP93 Number of run instructions completed. 4 Group 93 pm_cpi_stack6
PM_RUN_CYC_GRP93 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 93 pm_cpi_stack6
PM_GCT_NOSLOT_CYC_GRP94 Cycles when the Global Completion Table has no slots from this thread. 0 Group 94 pm_cpi_stack7
PM_GCT_NOSLOT_IC_MISS_GRP94 Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss. 1 Group 94 pm_cpi_stack7
PM_IOPS_DISP_GRP94 IOPS dispatched 2 Group 94 pm_cpi_stack7
PM_GCT_NOSLOT_BR_MPRED_GRP94 Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction. 3 Group 94 pm_cpi_stack7
PM_RUN_INST_CMPL_GRP94 Number of run instructions completed. 4 Group 94 pm_cpi_stack7
PM_RUN_CYC_GRP94 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 94 pm_cpi_stack7
PM_1PLUS_PPC_CMPL_GRP95 A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. 0 Group 95 pm_cpi_stack8
PM_CMPLU_STALL_STORE_GRP95 Completion stall due to store instruction 1 Group 95 pm_cpi_stack8
PM_INST_DISP_GRP95 Number of PowerPC instructions successfully dispatched. 2 Group 95 pm_cpi_stack8
PM_CMPLU_STALL_VECTOR_LONG_GRP95 completion stall due to long latency vector instruction 3 Group 95 pm_cpi_stack8
PM_RUN_INST_CMPL_GRP95 Number of run instructions completed. 4 Group 95 pm_cpi_stack8
PM_RUN_CYC_GRP95 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 95 pm_cpi_stack8
PM_CMPLU_STALL_THRD_GRP96 Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn 0 Group 96 pm_cpi_stack9
PM_CMPLU_STALL_DFU_GRP96 Completion stall caused by Decimal Floating Point Unit 1 Group 96 pm_cpi_stack9
PM_INST_CMPL_GRP96 Number of PowerPC Instructions that completed. 2 Group 96 pm_cpi_stack9
PM_CMPLU_STALL_COUNT_GRP96 Count of Cycles where a thread was not completing any groups , when the group completion table had entries for that thread. 3 Group 96 pm_cpi_stack9
PM_RUN_INST_CMPL_GRP96 Number of run instructions completed. 4 Group 96 pm_cpi_stack9
PM_RUN_CYC_GRP96 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 96 pm_cpi_stack9
PM_1PLUS_PPC_CMPL_GRP97 A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. 0 Group 97 pm_cpi_stack10
PM_CMPLU_STALL_DCACHE_MISS_GRP97 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU. 1 Group 97 pm_cpi_stack10
PM_L1_DCACHE_RELOAD_VALID_GRP97 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 97 pm_cpi_stack10
PM_CMPLU_STALL_ERAT_MISS_GRP97 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT. 3 Group 97 pm_cpi_stack10
PM_RUN_INST_CMPL_GRP97 Number of run instructions completed. 4 Group 97 pm_cpi_stack10
PM_RUN_CYC_GRP97 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 97 pm_cpi_stack10
PM_DATA_FROM_L2_GRP98 The processor's Data Cache was reloaded from the local L2 due to a demand load. 0 Group 98 pm_dsource1
PM_DATA_FROM_L3_GRP98 The processor's Data Cache was reloaded from the local L3 due to a demand load. 1 Group 98 pm_dsource1
PM_DATA_FROM_RMEM_GRP98 The processor's Data Cache was reloaded from memory attached to a different module than this processor is located on. 2 Group 98 pm_dsource1
PM_DATA_FROM_LMEM_GRP98 The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. 3 Group 98 pm_dsource1
PM_RUN_INST_CMPL_GRP98 Number of run instructions completed. 4 Group 98 pm_dsource1
PM_RUN_CYC_GRP98 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 98 pm_dsource1
PM_DATA_FROM_L3_GRP99 The processor's Data Cache was reloaded from the local L3 due to a demand load. 0 Group 99 pm_dsource2
PM_DATA_FROM_L31_SHR_GRP99 Data loaded from another L3 on same chip shared 1 Group 99 pm_dsource2
PM_DATA_FROM_LMEM_GRP99 The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. 2 Group 99 pm_dsource2
PM_DATA_FROM_L2MISS_GRP99 The processor's Data Cache was reloaded but not from the local L2. 3 Group 99 pm_dsource2
PM_RUN_INST_CMPL_GRP99 Number of run instructions completed. 4 Group 99 pm_dsource2
PM_RUN_CYC_GRP99 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 99 pm_dsource2
PM_DATA_FROM_DMEM_GRP100 The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load 0 Group 100 pm_dsource3
PM_DATA_FROM_L3MISS_GRP100 The processor's Data Cache was reloaded from beyond L3 due to a demand load 1 Group 100 pm_dsource3
PM_DATA_FROM_L21_MOD_GRP100 Data loaded from another L2 on same chip modified 2 Group 100 pm_dsource3
PM_DATA_FROM_L2MISS_GRP100 The processor's Data Cache was reloaded but not from the local L2. 3 Group 100 pm_dsource3
PM_RUN_INST_CMPL_GRP100 Number of run instructions completed. 4 Group 100 pm_dsource3
PM_RUN_CYC_GRP100 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 100 pm_dsource3
PM_DATA_FROM_L31_MOD_GRP101 Data loaded from another L3 on same chip modified 0 Group 101 pm_dsource4
PM_DATA_FROM_RL2L3_SHR_GRP101 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load 1 Group 101 pm_dsource4
PM_DATA_FROM_DL2L3_MOD_GRP101 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load 2 Group 101 pm_dsource4
PM_DATA_FROM_DL2L3_MOD_GRP101 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load 3 Group 101 pm_dsource4
PM_RUN_INST_CMPL_GRP101 Number of run instructions completed. 4 Group 101 pm_dsource4
PM_RUN_CYC_GRP101 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 101 pm_dsource4
PM_DATA_FROM_L31_SHR_GRP102 Data loaded from another L3 on same chip shared 0 Group 102 pm_dsource5
PM_DATA_FROM_DMEM_GRP102 The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load 1 Group 102 pm_dsource5
PM_DATA_FROM_DL2L3_SHR_GRP102 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load 2 Group 102 pm_dsource5
PM_DATA_FROM_L21_SHR_GRP102 Data loaded from another L2 on same chip shared 3 Group 102 pm_dsource5
PM_RUN_INST_CMPL_GRP102 Number of run instructions completed. 4 Group 102 pm_dsource5
PM_RUN_CYC_GRP102 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 102 pm_dsource5
PM_DATA_FROM_RL2L3_MOD_GRP103 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load 0 Group 103 pm_dsource6
PM_DATA_FROM_RL2L3_SHR_GRP103 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load 1 Group 103 pm_dsource6
PM_DATA_FROM_L21_SHR_GRP103 Data loaded from another L2 on same chip shared 2 Group 103 pm_dsource6
PM_DATA_FROM_L2MISS_GRP103 The processor's Data Cache was reloaded but not from the local L2. 3 Group 103 pm_dsource6
PM_RUN_INST_CMPL_GRP103 Number of run instructions completed. 4 Group 103 pm_dsource6
PM_RUN_CYC_GRP103 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 103 pm_dsource6
PM_DATA_FROM_RL2L3_SHR_GRP104 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load 0 Group 104 pm_dsource7
PM_DATA_FROM_L3MISS_GRP104 The processor's Data Cache was reloaded from beyond L3 due to a demand load 1 Group 104 pm_dsource7
PM_DATA_FROM_DL2L3_MOD_GRP104 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load 2 Group 104 pm_dsource7
PM_DATA_FROM_DL2L3_MOD_GRP104 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load 3 Group 104 pm_dsource7
PM_RUN_INST_CMPL_GRP104 Number of run instructions completed. 4 Group 104 pm_dsource7
PM_RUN_CYC_GRP104 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 104 pm_dsource7
PM_INST_CMPL_GRP105 Number of PowerPC Instructions that completed. 0 Group 105 pm_dsource8
PM_DATA_FROM_L3_GRP105 The processor's Data Cache was reloaded from the local L3 due to a demand load. 1 Group 105 pm_dsource8
PM_DATA_FROM_L3MISS_GRP105 The processor's Data Cache was reloaded from beyond L3 due to a demand load 2 Group 105 pm_dsource8
PM_DATA_FROM_LMEM_GRP105 The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. 3 Group 105 pm_dsource8
PM_RUN_INST_CMPL_GRP105 Number of run instructions completed. 4 Group 105 pm_dsource8
PM_RUN_CYC_GRP105 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 105 pm_dsource8
PM_DATA_FROM_L2_GRP106 The processor's Data Cache was reloaded from the local L2 due to a demand load. 0 Group 106 pm_dsource9
PM_DATA_FROM_L2MISS_GRP106 The processor's Data Cache was reloaded but not from the local L2. 1 Group 106 pm_dsource9
PM_L1_DCACHE_RELOAD_VALID_GRP106 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 106 pm_dsource9
PM_LD_MISS_L1_GRP106 Load references that miss the Level 1 Data cache. Combined unit 0 + 1. 3 Group 106 pm_dsource9
PM_RUN_INST_CMPL_GRP106 Number of run instructions completed. 4 Group 106 pm_dsource9
PM_RUN_CYC_GRP106 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 106 pm_dsource9
PM_DATA_FROM_RL2L3_MOD_GRP107 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load 0 Group 107 pm_dsource10
PM_DATA_FROM_RL2L3_SHR_GRP107 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load 1 Group 107 pm_dsource10
PM_DATA_FROM_DL2L3_SHR_GRP107 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load 2 Group 107 pm_dsource10
PM_DATA_FROM_DL2L3_MOD_GRP107 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load 3 Group 107 pm_dsource10
PM_RUN_INST_CMPL_GRP107 Number of run instructions completed. 4 Group 107 pm_dsource10
PM_RUN_CYC_GRP107 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 107 pm_dsource10
PM_DATA_FROM_L2_GRP108 The processor's Data Cache was reloaded from the local L2 due to a demand load. 0 Group 108 pm_dsource11
PM_DATA_FROM_L2MISS_GRP108 The processor's Data Cache was reloaded but not from the local L2. 1 Group 108 pm_dsource11
PM_DATA_FROM_L3MISS_GRP108 The processor's Data Cache was reloaded from beyond L3 due to a demand load 2 Group 108 pm_dsource11
PM_RUN_INST_CMPL_GRP108 Number of run instructions completed. 3 Group 108 pm_dsource11
PM_RUN_INST_CMPL_GRP108 Number of run instructions completed. 4 Group 108 pm_dsource11
PM_RUN_CYC_GRP108 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 108 pm_dsource11
PM_DATA_FROM_RL2L3_MOD_GRP109 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load 0 Group 109 pm_dsource12
PM_DATA_FROM_DMEM_GRP109 The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load 1 Group 109 pm_dsource12
PM_DATA_FROM_RMEM_GRP109 The processor's Data Cache was reloaded from memory attached to a different module than this processor is located on. 2 Group 109 pm_dsource12
PM_DATA_FROM_LMEM_GRP109 The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. 3 Group 109 pm_dsource12
PM_RUN_INST_CMPL_GRP109 Number of run instructions completed. 4 Group 109 pm_dsource12
PM_RUN_CYC_GRP109 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 109 pm_dsource12
PM_DERAT_MISS_4K_GRP110 A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload. 0 Group 110 pm_dsource13
PM_INST_CMPL_GRP110 Number of PowerPC Instructions that completed. 1 Group 110 pm_dsource13
PM_DATA_FROM_DL2L3_SHR_GRP110 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load 2 Group 110 pm_dsource13
PM_DATA_FROM_DL2L3_MOD_GRP110 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load 3 Group 110 pm_dsource13
PM_RUN_INST_CMPL_GRP110 Number of run instructions completed. 4 Group 110 pm_dsource13
PM_RUN_CYC_GRP110 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 110 pm_dsource13
PM_DATA_FROM_DMEM_GRP111 The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load 0 Group 111 pm_dsource14
PM_INST_CMPL_GRP111 Number of PowerPC Instructions that completed. 1 Group 111 pm_dsource14
PM_DATA_FROM_RMEM_GRP111 The processor's Data Cache was reloaded from memory attached to a different module than this processor is located on. 2 Group 111 pm_dsource14
PM_DATA_FROM_LMEM_GRP111 The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. 3 Group 111 pm_dsource14
PM_RUN_INST_CMPL_GRP111 Number of run instructions completed. 4 Group 111 pm_dsource14
PM_RUN_CYC_GRP111 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 111 pm_dsource14
PM_DATA_FROM_DMEM_GRP112 The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load 0 Group 112 pm_dsource15
PM_INST_CMPL_GRP112 Number of PowerPC Instructions that completed. 1 Group 112 pm_dsource15
PM_L1_DCACHE_RELOAD_VALID_GRP112 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 112 pm_dsource15
PM_DATA_FROM_LMEM_GRP112 The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. 3 Group 112 pm_dsource15
PM_RUN_INST_CMPL_GRP112 Number of run instructions completed. 4 Group 112 pm_dsource15
PM_RUN_CYC_GRP112 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 112 pm_dsource15
PM_INST_FROM_L2_GRP113 An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions 0 Group 113 pm_isource1
PM_INST_FROM_L3_GRP113 An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions 1 Group 113 pm_isource1
PM_INST_FROM_LMEM_GRP113 An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions 2 Group 113 pm_isource1
PM_INST_FROM_L2MISS_GRP113 An instruction fetch group was fetched from beyond the local L2. 3 Group 113 pm_isource1
PM_RUN_INST_CMPL_GRP113 Number of run instructions completed. 4 Group 113 pm_isource1
PM_RUN_CYC_GRP113 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 113 pm_isource1
PM_INST_FROM_L3_GRP114 An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions 0 Group 114 pm_isource2
PM_INST_FROM_DMEM_GRP114 An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions 1 Group 114 pm_isource2
PM_INST_FROM_DL2L3_MOD_GRP114 An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions 2 Group 114 pm_isource2
PM_INST_FROM_LMEM_GRP114 An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions 3 Group 114 pm_isource2
PM_RUN_INST_CMPL_GRP114 Number of run instructions completed. 4 Group 114 pm_isource2
PM_RUN_CYC_GRP114 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 114 pm_isource2
PM_INST_FROM_DMEM_GRP115 An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions 0 Group 115 pm_isource3
PM_INST_FROM_L3MISS_GRP115 An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. 1 Group 115 pm_isource3
PM_INST_FROM_DL2L3_SHR_GRP115 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions 2 Group 115 pm_isource3
PM_INST_FROM_DL2L3_MOD_GRP115 An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions 3 Group 115 pm_isource3
PM_RUN_INST_CMPL_GRP115 Number of run instructions completed. 4 Group 115 pm_isource3
PM_RUN_CYC_GRP115 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 115 pm_isource3
PM_INST_FROM_L31_MOD_GRP116 Instruction fetched from another L3 on same chip modified 0 Group 116 pm_isource4
PM_INST_FROM_L31_SHR_GRP116 Instruction fetched from another L3 on same chip shared 1 Group 116 pm_isource4
PM_INST_FROM_L21_MOD_GRP116 Instruction fetched from another L2 on same chip modified 2 Group 116 pm_isource4
PM_INST_FROM_L21_SHR_GRP116 Instruction fetched from another L2 on same chip shared 3 Group 116 pm_isource4
PM_RUN_INST_CMPL_GRP116 Number of run instructions completed. 4 Group 116 pm_isource4
PM_RUN_CYC_GRP116 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 116 pm_isource4
PM_INST_FROM_L31_SHR_GRP117 Instruction fetched from another L3 on same chip shared 0 Group 117 pm_isource5
PM_INST_FROM_RL2L3_SHR_GRP117 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions 1 Group 117 pm_isource5
PM_INST_FROM_L21_SHR_GRP117 Instruction fetched from another L2 on same chip shared 2 Group 117 pm_isource5
PM_INST_FROM_L2MISS_GRP117 An instruction fetch group was fetched from beyond the local L2. 3 Group 117 pm_isource5
PM_RUN_INST_CMPL_GRP117 Number of run instructions completed. 4 Group 117 pm_isource5
PM_RUN_CYC_GRP117 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 117 pm_isource5
PM_INST_FROM_PREF_GRP118 An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions 0 Group 118 pm_isource6
PM_INST_FROM_L3MISS_GRP118 An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. 1 Group 118 pm_isource6
PM_INST_FROM_LMEM_GRP118 An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions 2 Group 118 pm_isource6
PM_INST_FROM_L2MISS_GRP118 An instruction fetch group was fetched from beyond the local L2. 3 Group 118 pm_isource6
PM_RUN_INST_CMPL_GRP118 Number of run instructions completed. 4 Group 118 pm_isource6
PM_RUN_CYC_GRP118 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 118 pm_isource6
PM_INST_FROM_RL2L3_MOD_GRP119 An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions 0 Group 119 pm_isource7
PM_INST_FROM_RL2L3_SHR_GRP119 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions 1 Group 119 pm_isource7
PM_INST_FROM_DL2L3_SHR_GRP119 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions 2 Group 119 pm_isource7
PM_INST_FROM_DL2L3_MOD_GRP119 An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions 3 Group 119 pm_isource7
PM_RUN_INST_CMPL_GRP119 Number of run instructions completed. 4 Group 119 pm_isource7
PM_RUN_CYC_GRP119 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 119 pm_isource7
PM_INST_FROM_RL2L3_SHR_GRP120 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions 0 Group 120 pm_isource8
PM_INST_FROM_L3MISS_GRP120 An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. 1 Group 120 pm_isource8
PM_INST_FROM_LMEM_GRP120 An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions 2 Group 120 pm_isource8
PM_INST_FROM_L2MISS_GRP120 An instruction fetch group was fetched from beyond the local L2. 3 Group 120 pm_isource8
PM_RUN_INST_CMPL_GRP120 Number of run instructions completed. 4 Group 120 pm_isource8
PM_RUN_CYC_GRP120 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 120 pm_isource8
PM_INST_FROM_PREF_GRP121 An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions 0 Group 121 pm_isource9
PM_INST_FROM_DMEM_GRP121 An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions 1 Group 121 pm_isource9
PM_INST_FROM_RMEM_GRP121 An instruction fetch group was fetched from memory attached to a different module than this processor is located on. Fetch groups can contain up to 8 instructions 2 Group 121 pm_isource9
PM_INST_FROM_LMEM_GRP121 An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions 3 Group 121 pm_isource9
PM_RUN_INST_CMPL_GRP121 Number of run instructions completed. 4 Group 121 pm_isource9
PM_RUN_CYC_GRP121 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 121 pm_isource9
PM_INST_FROM_L2_GRP122 An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions 0 Group 122 pm_isource10
PM_INST_FROM_L3_GRP122 An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions 1 Group 122 pm_isource10
PM_INST_CMPL_GRP122 Number of PowerPC Instructions that completed. 2 Group 122 pm_isource10
PM_CYC_GRP122 Processor Cycles 3 Group 122 pm_isource10
PM_RUN_INST_CMPL_GRP122 Number of run instructions completed. 4 Group 122 pm_isource10
PM_RUN_CYC_GRP122 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 122 pm_isource10
PM_INST_FROM_RL2L3_MOD_GRP123 An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions 0 Group 123 pm_isource11
PM_INST_FROM_RL2L3_SHR_GRP123 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions 1 Group 123 pm_isource11
PM_INST_FROM_LMEM_GRP123 An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions 2 Group 123 pm_isource11
PM_INST_CMPL_GRP123 Number of PowerPC Instructions that completed. 3 Group 123 pm_isource11
PM_RUN_INST_CMPL_GRP123 Number of run instructions completed. 4 Group 123 pm_isource11
PM_RUN_CYC_GRP123 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 123 pm_isource11
PM_CYC_GRP124 Processor Cycles 0 Group 124 pm_isource12
PM_INST_CMPL_GRP124 Number of PowerPC Instructions that completed. 1 Group 124 pm_isource12
PM_INST_FROM_DL2L3_SHR_GRP124 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions 2 Group 124 pm_isource12
PM_INST_FROM_DL2L3_MOD_GRP124 An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions 3 Group 124 pm_isource12
PM_RUN_INST_CMPL_GRP124 Number of run instructions completed. 4 Group 124 pm_isource12
PM_RUN_CYC_GRP124 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 124 pm_isource12
PM_INST_FROM_DMEM_GRP125 An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions 0 Group 125 pm_isource13
PM_INST_CMPL_GRP125 Number of PowerPC Instructions that completed. 1 Group 125 pm_isource13
PM_INST_FROM_RMEM_GRP125 An instruction fetch group was fetched from memory attached to a different module than this processor is located on. Fetch groups can contain up to 8 instructions 2 Group 125 pm_isource13
PM_INST_FROM_LMEM_GRP125 An instruction fetch group was fetched from memory attached to the same module this processor is located on. Fetch groups can contain up to 8 instructions 3 Group 125 pm_isource13
PM_RUN_INST_CMPL_GRP125 Number of run instructions completed. 4 Group 125 pm_isource13
PM_RUN_CYC_GRP125 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 125 pm_isource13
PM_LSU_DC_PREF_STREAM_ALLOC_GRP126 D cache new prefetch stream allocated 0 Group 126 pm_prefetch1
PM_L3_PREF_LDST_GRP126 L3 cache prefetches LD + ST 1 Group 126 pm_prefetch1
PM_LSU_DC_PREF_STREAM_CONFIRM_GRP126 Dcache new prefetch stream confirmed 2 Group 126 pm_prefetch1
PM_L1_PREF_GRP126 A request to prefetch data into the L1 was made 3 Group 126 pm_prefetch1
PM_RUN_INST_CMPL_GRP126 Number of run instructions completed. 4 Group 126 pm_prefetch1
PM_RUN_CYC_GRP126 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 126 pm_prefetch1
PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM_GRP127 Dcache Strided prefetch stream confirmed (software + hardware) 0 Group 127 pm_prefetch2
PM_LD_REF_L1_GRP127 L1 D cache load references counted at finish 1 Group 127 pm_prefetch2
PM_LSU_FIN_GRP127 LSU Finished an instruction (up to 2 per cycle) 2 Group 127 pm_prefetch2
PM_LD_MISS_L1_GRP127 Load references that miss the Level 1 Data cache. Combined unit 0 + 1. 3 Group 127 pm_prefetch2
PM_RUN_INST_CMPL_GRP127 Number of run instructions completed. 4 Group 127 pm_prefetch2
PM_RUN_CYC_GRP127 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 127 pm_prefetch2
PM_VSU0_1FLOP_GRP128 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished 0 Group 128 pm_vsu0
PM_VSU1_1FLOP_GRP128 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished 1 Group 128 pm_vsu0
PM_VSU0_2FLOP_GRP128 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) 2 Group 128 pm_vsu0
PM_VSU1_2FLOP_GRP128 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) 3 Group 128 pm_vsu0
PM_RUN_INST_CMPL_GRP128 Number of run instructions completed. 4 Group 128 pm_vsu0
PM_RUN_CYC_GRP128 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 128 pm_vsu0
PM_VSU0_4FLOP_GRP129 four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) 0 Group 129 pm_vsu1
PM_VSU1_4FLOP_GRP129 four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) 1 Group 129 pm_vsu1
PM_VSU0_8FLOP_GRP129 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) 2 Group 129 pm_vsu1
PM_VSU1_8FLOP_GRP129 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) 3 Group 129 pm_vsu1
PM_RUN_INST_CMPL_GRP129 Number of run instructions completed. 4 Group 129 pm_vsu1
PM_RUN_CYC_GRP129 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 129 pm_vsu1
PM_VSU_2FLOP_GRP130 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) 0 Group 130 pm_vsu2
PM_VSU_2FLOP_DOUBLE_GRP130 DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg 1 Group 130 pm_vsu2
PM_VSU0_2FLOP_DOUBLE_GRP130 two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) 2 Group 130 pm_vsu2
PM_VSU1_2FLOP_DOUBLE_GRP130 two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) 3 Group 130 pm_vsu2
PM_RUN_INST_CMPL_GRP130 Number of run instructions completed. 4 Group 130 pm_vsu2
PM_RUN_CYC_GRP130 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 130 pm_vsu2
PM_VSU0_FMA_GRP131 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! 0 Group 131 pm_vsu3
PM_VSU1_FMA_GRP131 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! 1 Group 131 pm_vsu3
PM_VSU_FMA_GRP131 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! 2 Group 131 pm_vsu3
PM_INST_CMPL_GRP131 Number of PowerPC Instructions that completed. 3 Group 131 pm_vsu3
PM_RUN_INST_CMPL_GRP131 Number of run instructions completed. 4 Group 131 pm_vsu3
PM_RUN_CYC_GRP131 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 131 pm_vsu3
PM_VSU0_FMA_DOUBLE_GRP132 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) 0 Group 132 pm_vsu4
PM_VSU1_FMA_DOUBLE_GRP132 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) 1 Group 132 pm_vsu4
PM_VSU_FMA_DOUBLE_GRP132 DP vector version of fmadd,fnmadd,fmsub,fnmsub 2 Group 132 pm_vsu4
PM_INST_CMPL_GRP132 Number of PowerPC Instructions that completed. 3 Group 132 pm_vsu4
PM_RUN_INST_CMPL_GRP132 Number of run instructions completed. 4 Group 132 pm_vsu4
PM_RUN_CYC_GRP132 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 132 pm_vsu4
PM_VSU_VECTOR_DOUBLE_ISSUED_GRP133 Double Precision vector instruction issued on Pipe0 0 Group 133 pm_vsu5
PM_VSU0_VECT_DOUBLE_ISSUED_GRP133 Double Precision vector instruction issued on Pipe0 1 Group 133 pm_vsu5
PM_VSU1_VECT_DOUBLE_ISSUED_GRP133 Double Precision vector instruction issued on Pipe1 2 Group 133 pm_vsu5
PM_INST_CMPL_GRP133 Number of PowerPC Instructions that completed. 3 Group 133 pm_vsu5
PM_RUN_INST_CMPL_GRP133 Number of run instructions completed. 4 Group 133 pm_vsu5
PM_RUN_CYC_GRP133 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 133 pm_vsu5
PM_VSU_DENORM_GRP134 Vector or Scalar denorm operand 0 Group 134 pm_vsu6
PM_VSU0_DENORM_GRP134 VSU0 received denormalized data 1 Group 134 pm_vsu6
PM_VSU1_DENORM_GRP134 VSU1 received denormalized data 2 Group 134 pm_vsu6
PM_INST_CMPL_GRP134 Number of PowerPC Instructions that completed. 3 Group 134 pm_vsu6
PM_RUN_INST_CMPL_GRP134 Number of run instructions completed. 4 Group 134 pm_vsu6
PM_RUN_CYC_GRP134 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 134 pm_vsu6
PM_VSU_FIN_GRP135 VSU0 Finished an instruction 0 Group 135 pm_vsu7
PM_VSU0_FIN_GRP135 VSU0 Finished an instruction 1 Group 135 pm_vsu7
PM_VSU1_FIN_GRP135 VSU1 Finished an instruction 2 Group 135 pm_vsu7
PM_INST_CMPL_GRP135 Number of PowerPC Instructions that completed. 3 Group 135 pm_vsu7
PM_RUN_INST_CMPL_GRP135 Number of run instructions completed. 4 Group 135 pm_vsu7
PM_RUN_CYC_GRP135 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 135 pm_vsu7
PM_VSU_STF_GRP136 FPU store (SP or DP) issued on Pipe0 0 Group 136 pm_vsu8
PM_VSU0_STF_GRP136 FPU store (SP or DP) issued on Pipe0 1 Group 136 pm_vsu8
PM_VSU1_STF_GRP136 FPU store (SP or DP) issued on Pipe1 2 Group 136 pm_vsu8
PM_INST_CMPL_GRP136 Number of PowerPC Instructions that completed. 3 Group 136 pm_vsu8
PM_RUN_INST_CMPL_GRP136 Number of run instructions completed. 4 Group 136 pm_vsu8
PM_RUN_CYC_GRP136 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 136 pm_vsu8
PM_VSU_SINGLE_GRP137 Vector or Scalar single precision 0 Group 137 pm_vsu9
PM_VSU0_SINGLE_GRP137 VSU0 executed single precision instruction 1 Group 137 pm_vsu9
PM_VSU1_SINGLE_GRP137 VSU1 executed single precision instruction 2 Group 137 pm_vsu9
PM_VSU0_16FLOP_GRP137 Sixteen flops operation (SP vector versions of fdiv,fsqrt) 3 Group 137 pm_vsu9
PM_RUN_INST_CMPL_GRP137 Number of run instructions completed. 4 Group 137 pm_vsu9
PM_RUN_CYC_GRP137 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 137 pm_vsu9
PM_VSU_FSQRT_FDIV_GRP138 DP vector versions of fdiv,fsqrt 0 Group 138 pm_vsu10
PM_VSU0_FSQRT_FDIV_GRP138 four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! 1 Group 138 pm_vsu10
PM_VSU1_FSQRT_FDIV_GRP138 four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! 2 Group 138 pm_vsu10
PM_INST_CMPL_GRP138 Number of PowerPC Instructions that completed. 3 Group 138 pm_vsu10
PM_RUN_INST_CMPL_GRP138 Number of run instructions completed. 4 Group 138 pm_vsu10
PM_RUN_CYC_GRP138 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 138 pm_vsu10
PM_VSU_FSQRT_FDIV_DOUBLE_GRP139 DP vector versions of fdiv,fsqrt 0 Group 139 pm_vsu11
PM_VSU0_FSQRT_FDIV_DOUBLE_GRP139 eight flop DP vector operations (xvfdivdp, xvsqrtdp 1 Group 139 pm_vsu11
PM_VSU1_FSQRT_FDIV_DOUBLE_GRP139 eight flop DP vector operations (xvfdivdp, xvsqrtdp 2 Group 139 pm_vsu11
PM_INST_CMPL_GRP139 Number of PowerPC Instructions that completed. 3 Group 139 pm_vsu11
PM_RUN_INST_CMPL_GRP139 Number of run instructions completed. 4 Group 139 pm_vsu11
PM_RUN_CYC_GRP139 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 139 pm_vsu11
PM_VSU_SCALAR_DOUBLE_ISSUED_GRP140 Double Precision scalar instruction issued on Pipe0 0 Group 140 pm_vsu12
PM_VSU0_SCAL_DOUBLE_ISSUED_GRP140 Double Precision scalar instruction issued on Pipe0 1 Group 140 pm_vsu12
PM_VSU1_SCAL_DOUBLE_ISSUED_GRP140 Double Precision scalar instruction issued on Pipe1 2 Group 140 pm_vsu12
PM_INST_CMPL_GRP140 Number of PowerPC Instructions that completed. 3 Group 140 pm_vsu12
PM_RUN_INST_CMPL_GRP140 Number of run instructions completed. 4 Group 140 pm_vsu12
PM_RUN_CYC_GRP140 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 140 pm_vsu12
PM_VSU_SCALAR_SINGLE_ISSUED_GRP141 Single Precision scalar instruction issued on Pipe0 0 Group 141 pm_vsu13
PM_VSU0_SCAL_SINGLE_ISSUED_GRP141 Single Precision scalar instruction issued on Pipe0 1 Group 141 pm_vsu13
PM_VSU1_SCAL_SINGLE_ISSUED_GRP141 Single Precision scalar instruction issued on Pipe1 2 Group 141 pm_vsu13
PM_INST_CMPL_GRP141 Number of PowerPC Instructions that completed. 3 Group 141 pm_vsu13
PM_RUN_INST_CMPL_GRP141 Number of run instructions completed. 4 Group 141 pm_vsu13
PM_RUN_CYC_GRP141 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 141 pm_vsu13
PM_VSU_1FLOP_GRP142 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished 0 Group 142 pm_vsu14
PM_VSU_4FLOP_GRP142 four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) 1 Group 142 pm_vsu14
PM_VSU_8FLOP_GRP142 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) 2 Group 142 pm_vsu14
PM_VSU_2FLOP_GRP142 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) 3 Group 142 pm_vsu14
PM_RUN_INST_CMPL_GRP142 Number of run instructions completed. 4 Group 142 pm_vsu14
PM_RUN_CYC_GRP142 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 142 pm_vsu14
PM_VSU_VECTOR_SINGLE_ISSUED_GRP143 Single Precision vector instruction issued (executed) 0 Group 143 pm_vsu15
PM_VSU0_VECTOR_SP_ISSUED_GRP143 Single Precision vector instruction issued (executed) 1 Group 143 pm_vsu15
PM_VSU0_FPSCR_GRP143 Move to/from FPSCR type instruction issued on Pipe 0 2 Group 143 pm_vsu15
PM_INST_CMPL_GRP143 Number of PowerPC Instructions that completed. 3 Group 143 pm_vsu15
PM_RUN_INST_CMPL_GRP143 Number of run instructions completed. 4 Group 143 pm_vsu15
PM_RUN_CYC_GRP143 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 143 pm_vsu15
PM_VSU_SIMPLE_ISSUED_GRP144 Simple VMX instruction issued 0 Group 144 pm_vsu16
PM_VSU0_SIMPLE_ISSUED_GRP144 Simple VMX instruction issued 1 Group 144 pm_vsu16
PM_VSU0_COMPLEX_ISSUED_GRP144 Complex VMX instruction issued 2 Group 144 pm_vsu16
PM_VMX_RESULT_SAT_1_GRP144 Valid result with sat=1 3 Group 144 pm_vsu16
PM_RUN_INST_CMPL_GRP144 Number of run instructions completed. 4 Group 144 pm_vsu16
PM_RUN_CYC_GRP144 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 144 pm_vsu16
PM_VSU1_DD_ISSUED_GRP145 64BIT Decimal Issued on Pipe1 0 Group 145 pm_vsu17
PM_VSU1_DQ_ISSUED_GRP145 128BIT Decimal Issued on Pipe1 1 Group 145 pm_vsu17
PM_VSU1_PERMUTE_ISSUED_GRP145 Permute VMX Instruction Issued 2 Group 145 pm_vsu17
PM_VSU1_SQ_GRP145 Store Vector Issued on Pipe1 3 Group 145 pm_vsu17
PM_RUN_INST_CMPL_GRP145 Number of run instructions completed. 4 Group 145 pm_vsu17
PM_RUN_CYC_GRP145 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 145 pm_vsu17
PM_VSU_FCONV_GRP146 Convert instruction executed 0 Group 146 pm_vsu18
PM_VSU0_FCONV_GRP146 Convert instruction executed 1 Group 146 pm_vsu18
PM_VSU1_FCONV_GRP146 Convert instruction executed 2 Group 146 pm_vsu18
PM_INST_CMPL_GRP146 Number of PowerPC Instructions that completed. 3 Group 146 pm_vsu18
PM_RUN_INST_CMPL_GRP146 Number of run instructions completed. 4 Group 146 pm_vsu18
PM_RUN_CYC_GRP146 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 146 pm_vsu18
PM_VSU_FRSP_GRP147 Round to single precision instruction executed 0 Group 147 pm_vsu19
PM_VSU0_FRSP_GRP147 Round to single precision instruction executed 1 Group 147 pm_vsu19
PM_VSU1_FRSP_GRP147 Round to single precision instruction executed 2 Group 147 pm_vsu19
PM_INST_CMPL_GRP147 Number of PowerPC Instructions that completed. 3 Group 147 pm_vsu19
PM_RUN_INST_CMPL_GRP147 Number of run instructions completed. 4 Group 147 pm_vsu19
PM_RUN_CYC_GRP147 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 147 pm_vsu19
PM_VSU_FEST_GRP148 Estimate instruction executed 0 Group 148 pm_vsu20
PM_VSU0_FEST_GRP148 Estimate instruction executed 1 Group 148 pm_vsu20
PM_VSU1_FEST_GRP148 Estimate instruction executed 2 Group 148 pm_vsu20
PM_INST_CMPL_GRP148 Number of PowerPC Instructions that completed. 3 Group 148 pm_vsu20
PM_RUN_INST_CMPL_GRP148 Number of run instructions completed. 4 Group 148 pm_vsu20
PM_RUN_CYC_GRP148 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 148 pm_vsu20
PM_BRU_FIN_GRP149 The Branch execution unit finished an instruction 0 Group 149 pm_vsu21
PM_RUN_CYC_GRP149 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 149 pm_vsu21
PM_INST_CMPL_GRP149 Number of PowerPC Instructions that completed. 2 Group 149 pm_vsu21
PM_VSU_FIN_GRP149 VSU0 Finished an instruction 3 Group 149 pm_vsu21
PM_RUN_INST_CMPL_GRP149 Number of run instructions completed. 4 Group 149 pm_vsu21
PM_RUN_CYC_GRP149 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 149 pm_vsu21
PM_LSU_LDF_GRP150 LSU executed Floating Point load instruction. Combined Unit 0 + 1. 0 Group 150 pm_vsu22
PM_VSU_STF_GRP150 FPU store (SP or DP) issued on Pipe0 1 Group 150 pm_vsu22
PM_VSU_FMA_GRP150 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! 2 Group 150 pm_vsu22
PM_VSU_1FLOP_GRP150 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished 3 Group 150 pm_vsu22
PM_RUN_INST_CMPL_GRP150 Number of run instructions completed. 4 Group 150 pm_vsu22
PM_RUN_CYC_GRP150 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 150 pm_vsu22
PM_VSU_FSQRT_FDIV_GRP151 DP vector versions of fdiv,fsqrt 0 Group 151 pm_vsu23
PM_VSU_FIN_GRP151 VSU0 Finished an instruction 1 Group 151 pm_vsu23
PM_VSU_FMA_GRP151 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! 2 Group 151 pm_vsu23
PM_VSU_1FLOP_GRP151 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished 3 Group 151 pm_vsu23
PM_RUN_INST_CMPL_GRP151 Number of run instructions completed. 4 Group 151 pm_vsu23
PM_RUN_CYC_GRP151 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 151 pm_vsu23
PM_FLOP_GRP152 A floating point operation has completed 0 Group 152 pm_vsu24
PM_VSU_FIN_GRP152 VSU0 Finished an instruction 1 Group 152 pm_vsu24
PM_VSU_FEST_GRP152 Estimate instruction executed 2 Group 152 pm_vsu24
PM_VSU_1FLOP_GRP152 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished 3 Group 152 pm_vsu24
PM_RUN_INST_CMPL_GRP152 Number of run instructions completed. 4 Group 152 pm_vsu24
PM_RUN_CYC_GRP152 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 152 pm_vsu24
PM_VSU_STF_GRP153 FPU store (SP or DP) issued on Pipe0 0 Group 153 pm_vsu25
PM_VSU_FIN_GRP153 VSU0 Finished an instruction 1 Group 153 pm_vsu25
PM_VSU_FRSP_GRP153 Round to single precision instruction executed 2 Group 153 pm_vsu25
PM_VSU_FCONV_GRP153 Convert instruction executed 3 Group 153 pm_vsu25
PM_RUN_INST_CMPL_GRP153 Number of run instructions completed. 4 Group 153 pm_vsu25
PM_RUN_CYC_GRP153 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 153 pm_vsu25
PM_LSU_LMQ_FULL_CYC_GRP154 The Load Miss Queue was full. 0 Group 154 pm_lsu1
PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP154 Cycles when both the LMQ and SRQ are empty (LSU is idle) 1 Group 154 pm_lsu1
PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC_GRP154 ALL threads lsu empty (lmq and srq empty) 2 Group 154 pm_lsu1
PM_LSU_SRQ_EMPTY_CYC_GRP154 The Store Request Queue is empty 3 Group 154 pm_lsu1
PM_RUN_INST_CMPL_GRP154 Number of run instructions completed. 4 Group 154 pm_lsu1
PM_RUN_CYC_GRP154 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 154 pm_lsu1
PM_LSU_FX_FIN_GRP155 LSU Finished a FX operation (up to 2 per cycle) 0 Group 155 pm_lsu2
PM_LSU_NCST_GRP155 Non-cachable Stores sent to nest 1 Group 155 pm_lsu2
PM_LSU_FIN_GRP155 LSU Finished an instruction (up to 2 per cycle) 2 Group 155 pm_lsu2
PM_LSU_FLUSH_GRP155 A flush was initiated by the Load Store Unit. 3 Group 155 pm_lsu2
PM_RUN_INST_CMPL_GRP155 Number of run instructions completed. 4 Group 155 pm_lsu2
PM_RUN_CYC_GRP155 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 155 pm_lsu2
PM_LSU0_LMQ_LHR_MERGE_GRP156 LS0 Load Merged with another cacheline request 0 Group 156 pm_lsu_lmq
PM_LSU1_LMQ_LHR_MERGE_GRP156 LS1 Load Merge with another cacheline request 1 Group 156 pm_lsu_lmq
PM_LSU_LMQ_S0_VALID_GRP156 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). 2 Group 156 pm_lsu_lmq
PM_LSU_LMQ_FULL_CYC_GRP156 The Load Miss Queue was full. 3 Group 156 pm_lsu_lmq
PM_RUN_INST_CMPL_GRP156 Number of run instructions completed. 4 Group 156 pm_lsu_lmq
PM_RUN_CYC_GRP156 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 156 pm_lsu_lmq
PM_LSU_SRQ_STFWD_GRP157 Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1. 0 Group 157 pm_lsu_srq1
PM_LSU0_SRQ_STFWD_GRP157 Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. 1 Group 157 pm_lsu_srq1
PM_LSU1_SRQ_STFWD_GRP157 Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. 2 Group 157 pm_lsu_srq1
PM_INST_CMPL_GRP157 Number of PowerPC Instructions that completed. 3 Group 157 pm_lsu_srq1
PM_RUN_INST_CMPL_GRP157 Number of run instructions completed. 4 Group 157 pm_lsu_srq1
PM_RUN_CYC_GRP157 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 157 pm_lsu_srq1
PM_LSU_SRQ_SYNC_CYC_GRP158 Cycles that a sync instruction is active in the Store Request Queue. 0 Group 158 pm_lsu_srq2
PM_LSU_SRQ_SYNC_COUNT_GRP158 SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) 1 Group 158 pm_lsu_srq2
PM_LSU_SRQ_S0_VALID_GRP158 This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each). 2 Group 158 pm_lsu_srq2
PM_INST_CMPL_GRP158 Number of PowerPC Instructions that completed. 3 Group 158 pm_lsu_srq2
PM_RUN_INST_CMPL_GRP158 Number of run instructions completed. 4 Group 158 pm_lsu_srq2
PM_RUN_CYC_GRP158 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 158 pm_lsu_srq2
PM_LSU_SRQ_S0_VALID_GRP159 This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each). 0 Group 159 pm_lsu_s0_valid
PM_LSU_LRQ_S0_VALID_GRP159 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). 1 Group 159 pm_lsu_s0_valid
PM_LSU_LMQ_S0_VALID_GRP159 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). 2 Group 159 pm_lsu_s0_valid
PM_INST_CMPL_GRP159 Number of PowerPC Instructions that completed. 3 Group 159 pm_lsu_s0_valid
PM_RUN_INST_CMPL_GRP159 Number of run instructions completed. 4 Group 159 pm_lsu_s0_valid
PM_RUN_CYC_GRP159 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 159 pm_lsu_s0_valid
PM_LSU_LMQ_S0_ALLOC_GRP160 Slot 0 of LMQ valid 0 Group 160 pm_lsu_s0_alloc
PM_LSU_LRQ_S0_ALLOC_GRP160 Slot 0 of LRQ valid 1 Group 160 pm_lsu_s0_alloc
PM_LSU_SRQ_S0_ALLOC_GRP160 Slot 0 of SRQ valid 2 Group 160 pm_lsu_s0_alloc
PM_INST_CMPL_GRP160 Number of PowerPC Instructions that completed. 3 Group 160 pm_lsu_s0_alloc
PM_RUN_INST_CMPL_GRP160 Number of run instructions completed. 4 Group 160 pm_lsu_s0_alloc
PM_RUN_CYC_GRP160 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 160 pm_lsu_s0_alloc
PM_L1_PREF_GRP161 A request to prefetch data into the L1 was made 0 Group 161 pm_l1_pref
PM_LSU0_L1_PREF_GRP161 LS0 L1 cache data prefetches 1 Group 161 pm_l1_pref
PM_LSU1_L1_PREF_GRP161 LS1 L1 cache data prefetches 2 Group 161 pm_l1_pref
PM_INST_CMPL_GRP161 Number of PowerPC Instructions that completed. 3 Group 161 pm_l1_pref
PM_RUN_INST_CMPL_GRP161 Number of run instructions completed. 4 Group 161 pm_l1_pref
PM_RUN_CYC_GRP161 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 161 pm_l1_pref
PM_L2_LOC_GUESS_CORRECT_GRP162 L2 guess loc and guess was correct (ie data local) 0 Group 162 pm_l2_guess_1
PM_L2_LOC_GUESS_WRONG_GRP162 L2 guess loc and guess was not correct (ie data remote) 1 Group 162 pm_l2_guess_1
PM_CYC_GRP162 Processor Cycles 2 Group 162 pm_l2_guess_1
PM_INST_CMPL_GRP162 Number of PowerPC Instructions that completed. 3 Group 162 pm_l2_guess_1
PM_RUN_INST_CMPL_GRP162 Number of run instructions completed. 4 Group 162 pm_l2_guess_1
PM_RUN_CYC_GRP162 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 162 pm_l2_guess_1
PM_L2_GLOB_GUESS_CORRECT_GRP163 L2 guess glb and guess was correct (ie data remote) 0 Group 163 pm_l2_guess_2
PM_L2_GLOB_GUESS_WRONG_GRP163 L2 guess glb and guess was not correct (ie data local) 1 Group 163 pm_l2_guess_2
PM_CYC_GRP163 Processor Cycles 2 Group 163 pm_l2_guess_2
PM_INST_CMPL_GRP163 Number of PowerPC Instructions that completed. 3 Group 163 pm_l2_guess_2
PM_RUN_INST_CMPL_GRP163 Number of run instructions completed. 4 Group 163 pm_l2_guess_2
PM_RUN_CYC_GRP163 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 163 pm_l2_guess_2
PM_INST_IMC_MATCH_CMPL_GRP164 Number of instructions resulting from the marked instructions expansion that completed. 0 Group 164 pm_misc1
PM_INST_FROM_L1_GRP164 An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions 1 Group 164 pm_misc1
PM_INST_IMC_MATCH_DISP_GRP164 IMC Matches dispatched 2 Group 164 pm_misc1
PM_INST_CMPL_GRP164 Number of PowerPC Instructions that completed. 3 Group 164 pm_misc1
PM_RUN_INST_CMPL_GRP164 Number of run instructions completed. 4 Group 164 pm_misc1
PM_RUN_CYC_GRP164 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 164 pm_misc1
PM_EE_OFF_EXT_INT_GRP165 Cycles when an interrupt due to an external exception is pending but external exceptions were masked. 0 Group 165 pm_misc2
PM_EXT_INT_GRP165 An interrupt due to an external exception occurred 1 Group 165 pm_misc2
PM_TB_BIT_TRANS_GRP165 When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 2 Group 165 pm_misc2
PM_CYC_GRP165 Processor Cycles 3 Group 165 pm_misc2
PM_RUN_INST_CMPL_GRP165 Number of run instructions completed. 4 Group 165 pm_misc2
PM_RUN_CYC_GRP165 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 165 pm_misc2
PM_1PLUS_PPC_CMPL_GRP166 A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. 0 Group 166 pm_misc3
PM_HV_CYC_GRP166 Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0) 1 Group 166 pm_misc3
PM_INST_DISP_GRP166 Number of PowerPC instructions successfully dispatched. 2 Group 166 pm_misc3
PM_1PLUS_PPC_DISP_GRP166 A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. 3 Group 166 pm_misc3
PM_RUN_INST_CMPL_GRP166 Number of run instructions completed. 4 Group 166 pm_misc3
PM_RUN_CYC_GRP166 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 166 pm_misc3
PM_GRP_IC_MISS_NONSPEC_GRP167 Number of groups, counted at completion, that have encountered an instruction cache miss. 0 Group 167 pm_misc4
PM_GCT_NOSLOT_IC_MISS_GRP167 Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss. 1 Group 167 pm_misc4
PM_CYC_GRP167 Processor Cycles 2 Group 167 pm_misc4
PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP167 No slot in GCT caused by branch mispredict or I cache miss 3 Group 167 pm_misc4
PM_RUN_INST_CMPL_GRP167 Number of run instructions completed. 4 Group 167 pm_misc4
PM_RUN_CYC_GRP167 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 167 pm_misc4
PM_GRP_BR_MPRED_NONSPEC_GRP168 Group experienced non-speculative branch redirect 0 Group 168 pm_misc5
PM_BR_MPRED_CR_TA_GRP168 Branch mispredict - taken/not taken and target 1 Group 168 pm_misc5
PM_BR_MPRED_CCACHE_GRP168 A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. 2 Group 168 pm_misc5
PM_BR_MPRED_GRP168 A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both 3 Group 168 pm_misc5
PM_RUN_INST_CMPL_GRP168 Number of run instructions completed. 4 Group 168 pm_misc5
PM_RUN_CYC_GRP168 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 168 pm_misc5
PM_L1_DEMAND_WRITE_GRP169 Instruction Demand sectors wriittent into IL1 0 Group 169 pm_misc6
PM_IC_PREF_WRITE_GRP169 Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch. 1 Group 169 pm_misc6
PM_IC_WRITE_ALL_GRP169 Icache sectors written, prefetch + demand 2 Group 169 pm_misc6
PM_INST_CMPL_GRP169 Number of PowerPC Instructions that completed. 3 Group 169 pm_misc6
PM_RUN_INST_CMPL_GRP169 Number of run instructions completed. 4 Group 169 pm_misc6
PM_RUN_CYC_GRP169 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 169 pm_misc6
PM_THRESH_TIMEO_GRP170 The threshold timer expired 0 Group 170 pm_misc7
PM_HV_CYC_GRP170 Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0) 1 Group 170 pm_misc7
PM_CYC_GRP170 Processor Cycles 2 Group 170 pm_misc7
PM_IFU_FIN_GRP170 The Instruction Fetch Unit finished an instruction 3 Group 170 pm_misc7
PM_RUN_INST_CMPL_GRP170 Number of run instructions completed. 4 Group 170 pm_misc7
PM_RUN_CYC_GRP170 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 170 pm_misc7
PM_BR_MPRED_LSTACK_GRP171 Branch Mispredict due to Link Stack 0 Group 171 pm_misc8
PM_EXT_INT_GRP171 An interrupt due to an external exception occurred 1 Group 171 pm_misc8
PM_L1_DCACHE_RELOAD_VALID_GRP171 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 171 pm_misc8
PM_BR_MPRED_GRP171 A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both 3 Group 171 pm_misc8
PM_RUN_INST_CMPL_GRP171 Number of run instructions completed. 4 Group 171 pm_misc8
PM_RUN_CYC_GRP171 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 171 pm_misc8
PM_FLUSH_BR_MPRED_GRP172 A flush was caused by a branch mispredict. 0 Group 172 pm_misc9
PM_FLUSH_PARTIAL_GRP172 Partial flush 1 Group 172 pm_misc9
PM_LSU_SET_MPRED_GRP172 Line already in cache at reload time 2 Group 172 pm_misc9
PM_BR_MPRED_GRP172 A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both 3 Group 172 pm_misc9
PM_RUN_INST_CMPL_GRP172 Number of run instructions completed. 4 Group 172 pm_misc9
PM_RUN_CYC_GRP172 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 172 pm_misc9
PM_LSU_SRQ_FULL_CYC_GRP173 Cycles the Store Request Queue is full. 0 Group 173 pm_misc10
PM_LSU_DC_PREF_STREAM_ALLOC_GRP173 D cache new prefetch stream allocated 1 Group 173 pm_misc10
PM_L1_PREF_GRP173 A request to prefetch data into the L1 was made 2 Group 173 pm_misc10
PM_IBUF_FULL_CYC_GRP173 Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions. 3 Group 173 pm_misc10
PM_RUN_INST_CMPL_GRP173 Number of run instructions completed. 4 Group 173 pm_misc10
PM_RUN_CYC_GRP173 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 173 pm_misc10
PM_FLOP_GRP174 A floating point operation has completed 0 Group 174 pm_misc11
PM_CYC_GRP174 Processor Cycles 1 Group 174 pm_misc11
PM_GRP_CMPL_GRP174 A group completed. Microcoded instructions that span multiple groups will generate this event once per group. 2 Group 174 pm_misc11
PM_INST_CMPL_GRP174 Number of PowerPC Instructions that completed. 3 Group 174 pm_misc11
PM_RUN_INST_CMPL_GRP174 Number of run instructions completed. 4 Group 174 pm_misc11
PM_RUN_CYC_GRP174 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 174 pm_misc11
PM_INST_CMPL_GRP175 Number of PowerPC Instructions that completed. 0 Group 175 pm_misc_12
PM_ST_FIN_GRP175 Store requests sent to the nest. 1 Group 175 pm_misc_12
PM_TB_BIT_TRANS_GRP175 When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 2 Group 175 pm_misc_12
PM_FLUSH_GRP175 Flushes occurred including LSU and Branch flushes. 3 Group 175 pm_misc_12
PM_RUN_INST_CMPL_GRP175 Number of run instructions completed. 4 Group 175 pm_misc_12
PM_RUN_CYC_GRP175 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 175 pm_misc_12
PM_GCT_NOSLOT_CYC_GRP176 Cycles when the Global Completion Table has no slots from this thread. 0 Group 176 pm_misc_13
PM_ST_FIN_GRP176 Store requests sent to the nest. 1 Group 176 pm_misc_13
PM_DTLB_MISS_GRP176 Data TLB misses, all page sizes. 2 Group 176 pm_misc_13
PM_BR_MPRED_GRP176 A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both 3 Group 176 pm_misc_13
PM_RUN_INST_CMPL_GRP176 Number of run instructions completed. 4 Group 176 pm_misc_13
PM_RUN_CYC_GRP176 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 176 pm_misc_13
PM_CYC_GRP177 Processor Cycles 0 Group 177 pm_misc_14
PM_CYC_GRP177 Processor Cycles 1 Group 177 pm_misc_14
PM_INST_CMPL_GRP177 Number of PowerPC Instructions that completed. 2 Group 177 pm_misc_14
PM_IFU_FIN_GRP177 The Instruction Fetch Unit finished an instruction 3 Group 177 pm_misc_14
PM_RUN_INST_CMPL_GRP177 Number of run instructions completed. 4 Group 177 pm_misc_14
PM_RUN_CYC_GRP177 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 177 pm_misc_14
PM_LSU_DCACHE_RELOAD_VALID_GRP178 count per sector of lines reloaded in L1 (demand + prefetch) 0 Group 178 pm_misc_15
PM_CMPLU_STALL_STORE_GRP178 Completion stall due to store instruction 1 Group 178 pm_misc_15
PM_L1_DCACHE_RELOAD_VALID_GRP178 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 178 pm_misc_15
PM_CMPLU_STALL_VECTOR_LONG_GRP178 completion stall due to long latency vector instruction 3 Group 178 pm_misc_15
PM_RUN_INST_CMPL_GRP178 Number of run instructions completed. 4 Group 178 pm_misc_15
PM_RUN_CYC_GRP178 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 178 pm_misc_15
PM_CMPLU_STALL_END_GCT_NOSLOT_GRP179 Count ended because GCT went empty 0 Group 179 pm_misc_16
PM_LSU0_L1_SW_PREF_GRP179 LSU0 Software L1 Prefetches, including SW Transient Prefetches 1 Group 179 pm_misc_16
PM_LSU1_L1_SW_PREF_GRP179 LSU1 Software L1 Prefetches, including SW Transient Prefetches 2 Group 179 pm_misc_16
PM_CMPLU_STALL_IFU_GRP179 Completion stall due to IFU 3 Group 179 pm_misc_16
PM_RUN_INST_CMPL_GRP179 Number of run instructions completed. 4 Group 179 pm_misc_16
PM_RUN_CYC_GRP179 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 179 pm_misc_16
PM_BRU_FIN_GRP180 The Branch execution unit finished an instruction 0 Group 180 pm_misc_17
PM_ST_FIN_GRP180 Store requests sent to the nest. 1 Group 180 pm_misc_17
PM_MRK_PTEG_FROM_DL2L3_SHR_GRP180 A Page Table Entry was loaded into the ERAT from memory attached to a different module than this processor is located on due to a marked load or store. 2 Group 180 pm_misc_17
PM_CMPLU_STALL_BRU_GRP180 Completion stall due to BRU 3 Group 180 pm_misc_17
PM_RUN_INST_CMPL_GRP180 Number of run instructions completed. 4 Group 180 pm_misc_17
PM_RUN_CYC_GRP180 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 180 pm_misc_17
PM_SUSPENDED_GRP181 The counter is suspended (does not count) 0 Group 181 pm_suspend
PM_CYC_GRP181 Processor Cycles 1 Group 181 pm_suspend
PM_LWSYNC_GRP181 lwsync count (easier to use than IMC) 2 Group 181 pm_suspend
PM_INST_CMPL_GRP181 Number of PowerPC Instructions that completed. 3 Group 181 pm_suspend
PM_RUN_INST_CMPL_GRP181 Number of run instructions completed. 4 Group 181 pm_suspend
PM_RUN_CYC_GRP181 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 181 pm_suspend
PM_IOPS_CMPL_GRP182 Number of internal operations that completed. 0 Group 182 pm_iops
PM_CYC_GRP182 Processor Cycles 1 Group 182 pm_iops
PM_IOPS_DISP_GRP182 IOPS dispatched 2 Group 182 pm_iops
PM_INST_CMPL_GRP182 Number of PowerPC Instructions that completed. 3 Group 182 pm_iops
PM_RUN_INST_CMPL_GRP182 Number of run instructions completed. 4 Group 182 pm_iops
PM_RUN_CYC_GRP182 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 182 pm_iops
PM_LWSYNC_GRP183 lwsync count (easier to use than IMC) 0 Group 183 pm_sync
PM_CYC_GRP183 Processor Cycles 1 Group 183 pm_sync
PM_LWSYNC_HELD_GRP183 Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response. 2 Group 183 pm_sync
PM_INST_CMPL_GRP183 Number of PowerPC Instructions that completed. 3 Group 183 pm_sync
PM_RUN_INST_CMPL_GRP183 Number of run instructions completed. 4 Group 183 pm_sync
PM_RUN_CYC_GRP183 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 183 pm_sync
PM_CYC_GRP184 Processor Cycles 0 Group 184 pm_seg
PM_SEG_EXCEPTION_GRP184 ISEG + DSEG Exception 1 Group 184 pm_seg
PM_ISEG_GRP184 ISEG Exception 2 Group 184 pm_seg
PM_DSEG_GRP184 DSEG Exception 3 Group 184 pm_seg
PM_RUN_INST_CMPL_GRP184 Number of run instructions completed. 4 Group 184 pm_seg
PM_RUN_CYC_GRP184 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 184 pm_seg
PM_L3_HIT_GRP185 L3 Hits 0 Group 185 pm_l3_hit
PM_L3_LD_HIT_GRP185 L3 demand LD Hits 1 Group 185 pm_l3_hit
PM_L3_PREF_HIT_GRP185 L3 Prefetch Directory Hit 2 Group 185 pm_l3_hit
PM_L3_CO_L31_GRP185 L3 Castouts to L3.1 3 Group 185 pm_l3_hit
PM_RUN_INST_CMPL_GRP185 Number of run instructions completed. 4 Group 185 pm_l3_hit
PM_RUN_CYC_GRP185 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 185 pm_l3_hit
PM_SHL_DEALLOCATED_GRP186 SHL Table entry deallocated 0 Group 186 pm_shl
PM_SHL_CREATED_GRP186 SHL table entry Created 1 Group 186 pm_shl
PM_SHL_MERGED_GRP186 SHL table entry merged with existing 2 Group 186 pm_shl
PM_SHL_MATCH_GRP186 SHL Table Match 3 Group 186 pm_shl
PM_RUN_INST_CMPL_GRP186 Number of run instructions completed. 4 Group 186 pm_shl
PM_RUN_CYC_GRP186 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 186 pm_shl
PM_L3_PREF_LD_GRP187 L3 cache LD prefetches 0 Group 187 pm_l3_pref
PM_L3_PREF_ST_GRP187 L3 cache ST prefetches 1 Group 187 pm_l3_pref
PM_L3_PREF_LDST_GRP187 L3 cache prefetches LD + ST 2 Group 187 pm_l3_pref
PM_L1_PREF_GRP187 A request to prefetch data into the L1 was made 3 Group 187 pm_l3_pref
PM_RUN_INST_CMPL_GRP187 Number of run instructions completed. 4 Group 187 pm_l3_pref
PM_RUN_CYC_GRP187 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 187 pm_l3_pref
PM_L3_MISS_GRP188 L3 Misses 0 Group 188 pm_l3
PM_L3_LD_MISS_GRP188 L3 demand LD Miss 1 Group 188 pm_l3
PM_L3_PREF_MISS_GRP188 L3 Prefetch Directory Miss 2 Group 188 pm_l3
PM_L3_CO_MEM_GRP188 L3 Castouts to Memory 3 Group 188 pm_l3
PM_RUN_INST_CMPL_GRP188 Number of run instructions completed. 4 Group 188 pm_l3
PM_RUN_CYC_GRP188 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 188 pm_l3
PM_CYC_GRP189 Processor Cycles 0 Group 189 pm_streams1
PM_LSU_DC_PREF_STREAM_CONFIRM_GRP189 Dcache new prefetch stream confirmed 1 Group 189 pm_streams1
PM_LSU0_DC_PREF_STREAM_CONFIRM_GRP189 LS0 Dcache prefetch stream confirmed 2 Group 189 pm_streams1
PM_LSU1_DC_PREF_STREAM_CONFIRM_GRP189 LS1 'Dcache prefetch stream confirmed 3 Group 189 pm_streams1
PM_RUN_INST_CMPL_GRP189 Number of run instructions completed. 4 Group 189 pm_streams1
PM_RUN_CYC_GRP189 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 189 pm_streams1
PM_CYC_GRP190 Processor Cycles 0 Group 190 pm_streams2
PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM_GRP190 Dcache Strided prefetch stream confirmed (software + hardware) 1 Group 190 pm_streams2
PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE_GRP190 LS0 Dcache Strided prefetch stream confirmed 2 Group 190 pm_streams2
PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE_GRP190 LS1 Dcache Strided prefetch stream confirmed 3 Group 190 pm_streams2
PM_RUN_INST_CMPL_GRP190 Number of run instructions completed. 4 Group 190 pm_streams2
PM_RUN_CYC_GRP190 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 190 pm_streams2
PM_DC_PREF_DST_GRP191 A prefetch stream was started using the DST instruction. 0 Group 191 pm_streams3
PM_LSU_DC_PREF_STREAM_ALLOC_GRP191 D cache new prefetch stream allocated 1 Group 191 pm_streams3
PM_LSU0_DC_PREF_STREAM_ALLOC_GRP191 LS0 D cache new prefetch stream allocated 2 Group 191 pm_streams3
PM_LSU1_DC_PREF_STREAM_ALLOC_GRP191 LS 1 D cache new prefetch stream allocated 3 Group 191 pm_streams3
PM_RUN_INST_CMPL_GRP191 Number of run instructions completed. 4 Group 191 pm_streams3
PM_RUN_CYC_GRP191 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 191 pm_streams3
PM_LARX_LSU0_GRP192 A larx (lwarx or ldarx) was executed on side 0 0 Group 192 pm_larx
PM_LARX_LSU1_GRP192 A larx (lwarx or ldarx) was executed on side 1 1 Group 192 pm_larx
PM_CYC_GRP192 Processor Cycles 2 Group 192 pm_larx
PM_LARX_LSU_GRP192 Larx Finished 3 Group 192 pm_larx
PM_RUN_INST_CMPL_GRP192 Number of run instructions completed. 4 Group 192 pm_larx
PM_RUN_CYC_GRP192 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 192 pm_larx
PM_CYC_GRP193 Processor Cycles 0 Group 193 pm_ldf
PM_LSU_LDF_GRP193 LSU executed Floating Point load instruction. Combined Unit 0 + 1. 1 Group 193 pm_ldf
PM_LSU0_LDF_GRP193 A floating point load was executed by LSU0 2 Group 193 pm_ldf
PM_LSU1_LDF_GRP193 A floating point load was executed by LSU1 3 Group 193 pm_ldf
PM_RUN_INST_CMPL_GRP193 Number of run instructions completed. 4 Group 193 pm_ldf
PM_RUN_CYC_GRP193 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 193 pm_ldf
PM_CYC_GRP194 Processor Cycles 0 Group 194 pm_ldx
PM_LSU_LDX_GRP194 All Vector loads (vsx vector + vmx vector) 1 Group 194 pm_ldx
PM_LSU0_LDX_GRP194 LS0 Vector Loads 2 Group 194 pm_ldx
PM_LSU1_LDX_GRP194 LS1 Vector Loads 3 Group 194 pm_ldx
PM_RUN_INST_CMPL_GRP194 Number of run instructions completed. 4 Group 194 pm_ldx
PM_RUN_CYC_GRP194 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 194 pm_ldx
PM_L2_LD_GRP195 Data Load Count 0 Group 195 pm_l2_ld_st
PM_L2_ST_MISS_GRP195 Data Store Miss 1 Group 195 pm_l2_ld_st
PM_L3_PREF_HIT_GRP195 L3 Prefetch Directory Hit 2 Group 195 pm_l2_ld_st
PM_CYC_GRP195 Processor Cycles 3 Group 195 pm_l2_ld_st
PM_RUN_INST_CMPL_GRP195 Number of run instructions completed. 4 Group 195 pm_l2_ld_st
PM_RUN_CYC_GRP195 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 195 pm_l2_ld_st
PM_LARX_LSU_GRP196 Larx Finished 0 Group 196 pm_stcx
PM_LSU_REJECT_LHS_GRP196 The Load Store Unit rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1 1 Group 196 pm_stcx
PM_STCX_CMPL_GRP196 Conditional stores with reservation completed 2 Group 196 pm_stcx
PM_STCX_FAIL_GRP196 A stcx (stwcx or stdcx) failed 3 Group 196 pm_stcx
PM_RUN_INST_CMPL_GRP196 Number of run instructions completed. 4 Group 196 pm_stcx
PM_RUN_CYC_GRP196 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 196 pm_stcx
PM_BTAC_HIT_GRP197 BTAC Correct Prediction 0 Group 197 pm_btac
PM_BTAC_MISS_GRP197 BTAC Mispredicted 1 Group 197 pm_btac
PM_STCX_CMPL_GRP197 Conditional stores with reservation completed 2 Group 197 pm_btac
PM_STCX_FAIL_GRP197 A stcx (stwcx or stdcx) failed 3 Group 197 pm_btac
PM_RUN_INST_CMPL_GRP197 Number of run instructions completed. 4 Group 197 pm_btac
PM_RUN_CYC_GRP197 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 197 pm_btac
PM_BC_PLUS_8_CONV_GRP198 BC+8 Converted 0 Group 198 pm_br_bc
PM_BC_PLUS_8_RSLV_TAKEN_GRP198 BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled 1 Group 198 pm_br_bc
PM_CYC_GRP198 Processor Cycles 2 Group 198 pm_br_bc
PM_INST_CMPL_GRP198 Number of PowerPC Instructions that completed. 3 Group 198 pm_br_bc
PM_RUN_INST_CMPL_GRP198 Number of run instructions completed. 4 Group 198 pm_br_bc
PM_RUN_CYC_GRP198 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 198 pm_br_bc
PM_INST_IMC_MATCH_CMPL_GRP199 Number of instructions resulting from the marked instructions expansion that completed. 0 Group 199 pm_inst_imc
PM_INST_DISP_GRP199 Number of PowerPC instructions successfully dispatched. 1 Group 199 pm_inst_imc
PM_INST_IMC_MATCH_DISP_GRP199 IMC Matches dispatched 2 Group 199 pm_inst_imc
PM_INST_CMPL_GRP199 Number of PowerPC Instructions that completed. 3 Group 199 pm_inst_imc
PM_RUN_INST_CMPL_GRP199 Number of run instructions completed. 4 Group 199 pm_inst_imc
PM_RUN_CYC_GRP199 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 199 pm_inst_imc
PM_L2_LDST_GRP200 Data Load+Store Count 0 Group 200 pm_l2_misc1
PM_L2_LDST_MISS_GRP200 Data Load+Store Miss 1 Group 200 pm_l2_misc1
PM_L2_INST_MISS_GRP200 Instruction Load Misses 2 Group 200 pm_l2_misc1
PM_L2_DISP_ALL_GRP200 All successful LD/ST dispatches for this thread(i+d) 3 Group 200 pm_l2_misc1
PM_RUN_INST_CMPL_GRP200 Number of run instructions completed. 4 Group 200 pm_l2_misc1
PM_RUN_CYC_GRP200 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 200 pm_l2_misc1
PM_INST_CMPL_GRP201 Number of PowerPC Instructions that completed. 0 Group 201 pm_l2_misc2
PM_CYC_GRP201 Processor Cycles 1 Group 201 pm_l2_misc2
PM_L2_INST_GRP201 Instruction Load Count 2 Group 201 pm_l2_misc2
PM_L2_DISP_ALL_GRP201 All successful LD/ST dispatches for this thread(i+d) 3 Group 201 pm_l2_misc2
PM_RUN_INST_CMPL_GRP201 Number of run instructions completed. 4 Group 201 pm_l2_misc2
PM_RUN_CYC_GRP201 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 201 pm_l2_misc2
PM_INST_CMPL_GRP202 Number of PowerPC Instructions that completed. 0 Group 202 pm_l2_misc3
PM_CYC_GRP202 Processor Cycles 1 Group 202 pm_l2_misc3
PM_L2_SYS_PUMP_GRP202 RC req that was a global (aka system) pump attempt 2 Group 202 pm_l2_misc3
PM_RUN_INST_CMPL_GRP202 Number of run instructions completed. 3 Group 202 pm_l2_misc3
PM_RUN_INST_CMPL_GRP202 Number of run instructions completed. 4 Group 202 pm_l2_misc3
PM_RUN_CYC_GRP202 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 202 pm_l2_misc3
PM_INST_CMPL_GRP203 Number of PowerPC Instructions that completed. 0 Group 203 pm_l2_misc4
PM_CYC_GRP203 Processor Cycles 1 Group 203 pm_l2_misc4
PM_L2_SN_SX_I_DONE_GRP203 SNP dispatched and went from Sx or Tx to Ix 2 Group 203 pm_l2_misc4
PM_L2_SN_M_WR_DONE_GRP203 SNP dispatched for a write and was M 3 Group 203 pm_l2_misc4
PM_RUN_INST_CMPL_GRP203 Number of run instructions completed. 4 Group 203 pm_l2_misc4
PM_RUN_CYC_GRP203 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 203 pm_l2_misc4
PM_INST_CMPL_GRP204 Number of PowerPC Instructions that completed. 0 Group 204 pm_l2_misc5
PM_CYC_GRP204 Processor Cycles 1 Group 204 pm_l2_misc5
PM_L2_NODE_PUMP_GRP204 RC req that was a local (aka node) pump attempt 2 Group 204 pm_l2_misc5
PM_RUN_INST_CMPL_GRP204 Number of run instructions completed. 3 Group 204 pm_l2_misc5
PM_RUN_INST_CMPL_GRP204 Number of run instructions completed. 4 Group 204 pm_l2_misc5
PM_RUN_CYC_GRP204 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 204 pm_l2_misc5
PM_INST_CMPL_GRP205 Number of PowerPC Instructions that completed. 0 Group 205 pm_l2_misc6
PM_RUN_CYC_GRP205 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 205 pm_l2_misc6
PM_CYC_GRP205 Processor Cycles 2 Group 205 pm_l2_misc6
PM_L2_SN_M_RD_DONE_GRP205 SNP dispatched for a read and was M 3 Group 205 pm_l2_misc6
PM_RUN_INST_CMPL_GRP205 Number of run instructions completed. 4 Group 205 pm_l2_misc6
PM_RUN_CYC_GRP205 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 205 pm_l2_misc6
PM_IERAT_MISS_GRP206 A translation request missed the Instruction Effective to Real Address Translation (ERAT) table 0 Group 206 pm_ierat
PM_IERAT_XLATE_WR_16MPLUS_GRP206 large page 16M+ 1 Group 206 pm_ierat
PM_IERAT_WR_64K_GRP206 large page 64k 2 Group 206 pm_ierat
PM_INST_CMPL_GRP206 Number of PowerPC Instructions that completed. 3 Group 206 pm_ierat
PM_RUN_INST_CMPL_GRP206 Number of run instructions completed. 4 Group 206 pm_ierat
PM_RUN_CYC_GRP206 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 206 pm_ierat
PM_DISP_CLB_HELD_GRP207 CLB Hold: Any Reason 0 Group 207 pm_disp_clb
PM_DISP_CLB_HELD_SB_GRP207 Dispatch/CLB Hold: Scoreboard 1 Group 207 pm_disp_clb
PM_CYC_GRP207 Processor Cycles 2 Group 207 pm_disp_clb
PM_INST_CMPL_GRP207 Number of PowerPC Instructions that completed. 3 Group 207 pm_disp_clb
PM_RUN_INST_CMPL_GRP207 Number of run instructions completed. 4 Group 207 pm_disp_clb
PM_RUN_CYC_GRP207 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 207 pm_disp_clb
PM_CYC_GRP208 Processor Cycles 0 Group 208 pm_dpu
PM_DPU_HELD_POWER_GRP208 Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time 1 Group 208 pm_dpu
PM_DISP_WT_GRP208 Dispatched Starved (not held, nothing to dispatch) 2 Group 208 pm_dpu
PM_INST_CMPL_GRP208 Number of PowerPC Instructions that completed. 3 Group 208 pm_dpu
PM_RUN_INST_CMPL_GRP208 Number of run instructions completed. 4 Group 208 pm_dpu
PM_RUN_CYC_GRP208 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 208 pm_dpu
PM_RUN_SPURR_GRP209 Run SPURR 0 Group 209 pm_cpu_util
PM_RUN_CYC_GRP209 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 209 pm_cpu_util
PM_CYC_GRP209 Processor Cycles 2 Group 209 pm_cpu_util
PM_RUN_PURR_GRP209 The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. 3 Group 209 pm_cpu_util
PM_RUN_INST_CMPL_GRP209 Number of run instructions completed. 4 Group 209 pm_cpu_util
PM_RUN_CYC_GRP209 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 209 pm_cpu_util
PM_PMC4_OVERFLOW_GRP210 Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. 0 Group 210 pm_overflow1
PM_PMC1_OVERFLOW_GRP210 Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. 1 Group 210 pm_overflow1
PM_PMC2_OVERFLOW_GRP210 Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. 2 Group 210 pm_overflow1
PM_PMC3_OVERFLOW_GRP210 Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. 3 Group 210 pm_overflow1
PM_RUN_INST_CMPL_GRP210 Number of run instructions completed. 4 Group 210 pm_overflow1
PM_RUN_CYC_GRP210 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 210 pm_overflow1
PM_PMC5_OVERFLOW_GRP211 Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. 0 Group 211 pm_overflow2
PM_PMC1_OVERFLOW_GRP211 Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. 1 Group 211 pm_overflow2
PM_PMC6_OVERFLOW_GRP211 Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. 2 Group 211 pm_overflow2
PM_PMC3_OVERFLOW_GRP211 Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. 3 Group 211 pm_overflow2
PM_RUN_INST_CMPL_GRP211 Number of run instructions completed. 4 Group 211 pm_overflow2
PM_RUN_CYC_GRP211 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 211 pm_overflow2
PM_PMC4_REWIND_GRP212 PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value. 0 Group 212 pm_rewind
PM_RUN_CYC_GRP212 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 212 pm_rewind
PM_PMC2_REWIND_GRP212 PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value. 2 Group 212 pm_rewind
PM_INST_CMPL_GRP212 Number of PowerPC Instructions that completed. 3 Group 212 pm_rewind
PM_RUN_INST_CMPL_GRP212 Number of run instructions completed. 4 Group 212 pm_rewind
PM_RUN_CYC_GRP212 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 212 pm_rewind
PM_PMC2_SAVED_GRP213 PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register. 0 Group 213 pm_saved
PM_RUN_CYC_GRP213 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 213 pm_saved
PM_PMC4_SAVED_GRP213 PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register. 2 Group 213 pm_saved
PM_INST_CMPL_GRP213 Number of PowerPC Instructions that completed. 3 Group 213 pm_saved
PM_RUN_INST_CMPL_GRP213 Number of run instructions completed. 4 Group 213 pm_saved
PM_RUN_CYC_GRP213 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 213 pm_saved
PM_FLUSH_DISP_TLBIE_GRP214 Dispatch Flush: TLBIE 0 Group 214 pm_tlbie
PM_DISP_CLB_HELD_TLBIE_GRP214 Dispatch Hold: Due to TLBIE 1 Group 214 pm_tlbie
PM_SNOOP_TLBIE_GRP214 A tlbie was snooped from another processor. 2 Group 214 pm_tlbie
PM_INST_CMPL_GRP214 Number of PowerPC Instructions that completed. 3 Group 214 pm_tlbie
PM_RUN_INST_CMPL_GRP214 Number of run instructions completed. 4 Group 214 pm_tlbie
PM_RUN_CYC_GRP214 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 214 pm_tlbie
PM_IERAT_MISS_GRP215 A translation request missed the Instruction Effective to Real Address Translation (ERAT) table 0 Group 215 pm_id_miss_erat_l1
PM_L1_ICACHE_MISS_GRP215 An instruction fetch request missed the L1 cache. 1 Group 215 pm_id_miss_erat_l1
PM_ST_MISS_L1_GRP215 A store missed the dcache. Combined Unit 0 + 1. 2 Group 215 pm_id_miss_erat_l1
PM_LD_MISS_L1_GRP215 Load references that miss the Level 1 Data cache. Combined unit 0 + 1. 3 Group 215 pm_id_miss_erat_l1
PM_RUN_INST_CMPL_GRP215 Number of run instructions completed. 4 Group 215 pm_id_miss_erat_l1
PM_RUN_CYC_GRP215 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 215 pm_id_miss_erat_l1
PM_CYC_GRP216 Processor Cycles 0 Group 216 pm_id_miss_erat_tlab
PM_LSU_DERAT_MISS_GRP216 Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. 1 Group 216 pm_id_miss_erat_tlab
PM_DTLB_MISS_GRP216 Data TLB misses, all page sizes. 2 Group 216 pm_id_miss_erat_tlab
PM_ITLB_MISS_GRP216 A TLB miss for an Instruction Fetch has occurred 3 Group 216 pm_id_miss_erat_tlab
PM_RUN_INST_CMPL_GRP216 Number of run instructions completed. 4 Group 216 pm_id_miss_erat_tlab
PM_RUN_CYC_GRP216 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 216 pm_id_miss_erat_tlab
PM_ANY_THRD_RUN_CYC_GRP217 One of threads in run_cycles 0 Group 217 pm_compat_utilization1
PM_RUN_CYC_GRP217 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 217 pm_compat_utilization1
PM_CYC_GRP217 Processor Cycles 2 Group 217 pm_compat_utilization1
PM_RUN_PURR_GRP217 The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. 3 Group 217 pm_compat_utilization1
PM_RUN_INST_CMPL_GRP217 Number of run instructions completed. 4 Group 217 pm_compat_utilization1
PM_RUN_CYC_GRP217 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 217 pm_compat_utilization1
PM_FLOP_GRP218 A floating point operation has completed 0 Group 218 pm_compat_utilization2
PM_RUN_CYC_GRP218 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 218 pm_compat_utilization2
PM_CYC_GRP218 Processor Cycles 2 Group 218 pm_compat_utilization2
PM_RUN_INST_CMPL_GRP218 Number of run instructions completed. 3 Group 218 pm_compat_utilization2
PM_RUN_INST_CMPL_GRP218 Number of run instructions completed. 4 Group 218 pm_compat_utilization2
PM_RUN_CYC_GRP218 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 218 pm_compat_utilization2
PM_1PLUS_PPC_CMPL_GRP219 A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. 0 Group 219 pm_compat_cpi_1plus_ppc
PM_RUN_CYC_GRP219 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 219 pm_compat_cpi_1plus_ppc
PM_INST_DISP_GRP219 Number of PowerPC instructions successfully dispatched. 2 Group 219 pm_compat_cpi_1plus_ppc
PM_1PLUS_PPC_DISP_GRP219 A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. 3 Group 219 pm_compat_cpi_1plus_ppc
PM_RUN_INST_CMPL_GRP219 Number of run instructions completed. 4 Group 219 pm_compat_cpi_1plus_ppc
PM_RUN_CYC_GRP219 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 219 pm_compat_cpi_1plus_ppc
PM_INST_CMPL_GRP220 Number of PowerPC Instructions that completed. 0 Group 220 pm_compat_l1_dcache_load_store_miss
PM_ST_FIN_GRP220 Store requests sent to the nest. 1 Group 220 pm_compat_l1_dcache_load_store_miss
PM_ST_MISS_L1_GRP220 A store missed the dcache. Combined Unit 0 + 1. 2 Group 220 pm_compat_l1_dcache_load_store_miss
PM_LD_MISS_L1_GRP220 Load references that miss the Level 1 Data cache. Combined unit 0 + 1. 3 Group 220 pm_compat_l1_dcache_load_store_miss
PM_RUN_INST_CMPL_GRP220 Number of run instructions completed. 4 Group 220 pm_compat_l1_dcache_load_store_miss
PM_RUN_CYC_GRP220 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 220 pm_compat_l1_dcache_load_store_miss
PM_INST_CMPL_GRP221 Number of PowerPC Instructions that completed. 0 Group 221 pm_compat_l1_cache_load
PM_DATA_FROM_L2MISS_GRP221 The processor's Data Cache was reloaded but not from the local L2. 1 Group 221 pm_compat_l1_cache_load
PM_L1_DCACHE_RELOAD_VALID_GRP221 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. 2 Group 221 pm_compat_l1_cache_load
PM_LD_MISS_L1_GRP221 Load references that miss the Level 1 Data cache. Combined unit 0 + 1. 3 Group 221 pm_compat_l1_cache_load
PM_RUN_INST_CMPL_GRP221 Number of run instructions completed. 4 Group 221 pm_compat_l1_cache_load
PM_RUN_CYC_GRP221 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 221 pm_compat_l1_cache_load
PM_IERAT_MISS_GRP222 A translation request missed the Instruction Effective to Real Address Translation (ERAT) table 0 Group 222 pm_compat_instruction_directory
PM_L1_ICACHE_MISS_GRP222 An instruction fetch request missed the L1 cache. 1 Group 222 pm_compat_instruction_directory
PM_INST_CMPL_GRP222 Number of PowerPC Instructions that completed. 2 Group 222 pm_compat_instruction_directory
PM_ITLB_MISS_GRP222 A TLB miss for an Instruction Fetch has occurred 3 Group 222 pm_compat_instruction_directory
PM_RUN_INST_CMPL_GRP222 Number of run instructions completed. 4 Group 222 pm_compat_instruction_directory
PM_RUN_CYC_GRP222 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 222 pm_compat_instruction_directory
PM_SUSPENDED_GRP223 The counter is suspended (does not count) 0 Group 223 pm_compat_suspend
PM_SUSPENDED_GRP223 The counter is suspended (does not count) 1 Group 223 pm_compat_suspend
PM_SUSPENDED_GRP223 The counter is suspended (does not count) 2 Group 223 pm_compat_suspend
PM_SUSPENDED_GRP223 The counter is suspended (does not count) 3 Group 223 pm_compat_suspend
PM_RUN_INST_CMPL_GRP223 Number of run instructions completed. 4 Group 223 pm_compat_suspend
PM_RUN_CYC_GRP223 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 223 pm_compat_suspend
PM_INST_CMPL_GRP224 Number of PowerPC Instructions that completed. 0 Group 224 pm_compat_misc_events1
PM_EXT_INT_GRP224 An interrupt due to an external exception occurred 1 Group 224 pm_compat_misc_events1
PM_TB_BIT_TRANS_GRP224 When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 2 Group 224 pm_compat_misc_events1
PM_CYC_GRP224 Processor Cycles 3 Group 224 pm_compat_misc_events1
PM_RUN_INST_CMPL_GRP224 Number of run instructions completed. 4 Group 224 pm_compat_misc_events1
PM_RUN_CYC_GRP224 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 224 pm_compat_misc_events1
PM_INST_IMC_MATCH_CMPL_GRP225 Number of instructions resulting from the marked instructions expansion that completed. 0 Group 225 pm_compat_misc_events2
PM_INST_DISP_GRP225 Number of PowerPC instructions successfully dispatched. 1 Group 225 pm_compat_misc_events2
PM_THRD_CONC_RUN_INST_GRP225 Instructions completed by this thread when both threads had their run latches set. 2 Group 225 pm_compat_misc_events2
PM_FLUSH_GRP225 Flushes occurred including LSU and Branch flushes. 3 Group 225 pm_compat_misc_events2
PM_RUN_INST_CMPL_GRP225 Number of run instructions completed. 4 Group 225 pm_compat_misc_events2
PM_RUN_CYC_GRP225 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 225 pm_compat_misc_events2
PM_GCT_NOSLOT_CYC_GRP226 Cycles when the Global Completion Table has no slots from this thread. 0 Group 226 pm_compat_misc_events3
PM_INST_DISP_GRP226 Number of PowerPC instructions successfully dispatched. 1 Group 226 pm_compat_misc_events3
PM_CYC_GRP226 Processor Cycles 2 Group 226 pm_compat_misc_events3
PM_BR_MPRED_GRP226 A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both 3 Group 226 pm_compat_misc_events3
PM_RUN_INST_CMPL_GRP226 Number of run instructions completed. 4 Group 226 pm_compat_misc_events3
PM_RUN_CYC_GRP226 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 226 pm_compat_misc_events3
PM_MRK_BR_TAKEN_GRP227 A marked branch was taken 0 Group 227 pm_mrk_br
PM_MRK_LD_MISS_L1_GRP227 Marked L1 D cache load misses 1 Group 227 pm_mrk_br
PM_MRK_BR_MPRED_GRP227 A marked branch was mispredicted 2 Group 227 pm_mrk_br
PM_INST_CMPL_GRP227 Number of PowerPC Instructions that completed. 3 Group 227 pm_mrk_br
PM_RUN_INST_CMPL_GRP227 Number of run instructions completed. 4 Group 227 pm_mrk_br
PM_RUN_CYC_GRP227 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 227 pm_mrk_br
PM_MRK_DATA_FROM_DMEM_GRP228 The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load. 0 Group 228 pm_mrk_dsource1
PM_MRK_DATA_FROM_DMEM_CYC_GRP228 Marked ld latency Data Source 1110 (Distant Memory) 1 Group 228 pm_mrk_dsource1
PM_INST_CMPL_GRP228 Number of PowerPC Instructions that completed. 2 Group 228 pm_mrk_dsource1
PM_MRK_DATA_FROM_L2MISS_GRP228 DL1 was reloaded from beyond L2 due to a marked demand load. 3 Group 228 pm_mrk_dsource1
PM_RUN_INST_CMPL_GRP228 Number of run instructions completed. 4 Group 228 pm_mrk_dsource1
PM_RUN_CYC_GRP228 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 228 pm_mrk_dsource1
PM_MRK_LD_MISS_EXPOSED_CYC_GRP229 Marked Load exposed Miss 0 Group 229 pm_mrk_dsource2
PM_INST_CMPL_GRP229 Number of PowerPC Instructions that completed. 1 Group 229 pm_mrk_dsource2
PM_MRK_DATA_FROM_L21_MOD_GRP229 Marked data loaded from another L2 on same chip modified 2 Group 229 pm_mrk_dsource2
PM_MRK_DATA_FROM_L21_MOD_CYC_GRP229 Marked ld latency Data source 0101 (L2.1 M same chip) 3 Group 229 pm_mrk_dsource2
PM_RUN_INST_CMPL_GRP229 Number of run instructions completed. 4 Group 229 pm_mrk_dsource2
PM_RUN_CYC_GRP229 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 229 pm_mrk_dsource2
PM_MRK_DATA_FROM_L3_GRP230 The processor's Data Cache was reloaded from the local L3 due to a marked load. 0 Group 230 pm_mrk_dsource3
PM_MRK_DATA_FROM_L3MISS_GRP230 DL1 was reloaded from beyond L3 due to a marked load. 1 Group 230 pm_mrk_dsource3
PM_INST_CMPL_GRP230 Number of PowerPC Instructions that completed. 2 Group 230 pm_mrk_dsource3
PM_MRK_DATA_FROM_L3_CYC_GRP230 Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. 3 Group 230 pm_mrk_dsource3
PM_RUN_INST_CMPL_GRP230 Number of run instructions completed. 4 Group 230 pm_mrk_dsource3
PM_RUN_CYC_GRP230 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 230 pm_mrk_dsource3
PM_INST_CMPL_GRP231 Number of PowerPC Instructions that completed. 0 Group 231 pm_mrk_dsource4
PM_MRK_DATA_FROM_LMEM_CYC_GRP231 Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. 1 Group 231 pm_mrk_dsource4
PM_MRK_DATA_FROM_LMEM_GRP231 The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this processor is located on. 2 Group 231 pm_mrk_dsource4
PM_DATA_FROM_LMEM_GRP231 The processor's Data Cache was reloaded from memory attached to the same module this processor is located on. 3 Group 231 pm_mrk_dsource4
PM_RUN_INST_CMPL_GRP231 Number of run instructions completed. 4 Group 231 pm_mrk_dsource4
PM_RUN_CYC_GRP231 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 231 pm_mrk_dsource4
PM_MRK_DATA_FROM_L31_MOD_GRP232 Marked data loaded from another L3 on same chip modified 0 Group 232 pm_mrk_dsource5
PM_INST_CMPL_GRP232 Number of PowerPC Instructions that completed. 1 Group 232 pm_mrk_dsource5
PM_MRK_INST_FIN_GRP232 One of the execution units finished a marked instruction. Instructions that finish may not necessary complete 2 Group 232 pm_mrk_dsource5
PM_MRK_DATA_FROM_L31_MOD_CYC_GRP232 Marked ld latency Data source 0111 (L3.1 M same chip) 3 Group 232 pm_mrk_dsource5
PM_RUN_INST_CMPL_GRP232 Number of run instructions completed. 4 Group 232 pm_mrk_dsource5
PM_RUN_CYC_GRP232 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 232 pm_mrk_dsource5
PM_MRK_LD_MISS_EXPOSED_CYC_COUNT_GRP233 Marked Load exposed Miss (use edge detect to count #) 0 Group 233 pm_mrk_dsource6
PM_MRK_DATA_FROM_L21_SHR_CYC_GRP233 Marked load latency Data source 0100 (L2.1 S) 1 Group 233 pm_mrk_dsource6
PM_MRK_DATA_FROM_L21_SHR_GRP233 Marked data loaded from another L2 on same chip shared 2 Group 233 pm_mrk_dsource6
PM_INST_CMPL_GRP233 Number of PowerPC Instructions that completed. 3 Group 233 pm_mrk_dsource6
PM_RUN_INST_CMPL_GRP233 Number of run instructions completed. 4 Group 233 pm_mrk_dsource6
PM_RUN_CYC_GRP233 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 233 pm_mrk_dsource6
PM_MRK_DATA_FROM_L2_GRP234 The processor's Data Cache was reloaded from the local L2 due to a marked load. 0 Group 234 pm_mrk_dsource7
PM_MRK_DATA_FROM_L2_CYC_GRP234 Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. 1 Group 234 pm_mrk_dsource7
PM_INST_CMPL_GRP234 Number of PowerPC Instructions that completed. 2 Group 234 pm_mrk_dsource7
PM_MRK_DATA_FROM_L2MISS_GRP234 DL1 was reloaded from beyond L2 due to a marked demand load. 3 Group 234 pm_mrk_dsource7
PM_RUN_INST_CMPL_GRP234 Number of run instructions completed. 4 Group 234 pm_mrk_dsource7
PM_RUN_CYC_GRP234 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 234 pm_mrk_dsource7
PM_MRK_DATA_FROM_RL2L3_MOD_GRP235 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a marked load. 0 Group 235 pm_mrk_dsource8
PM_MRK_DATA_FROM_L3MISS_GRP235 DL1 was reloaded from beyond L3 due to a marked load. 1 Group 235 pm_mrk_dsource8
PM_INST_CMPL_GRP235 Number of PowerPC Instructions that completed. 2 Group 235 pm_mrk_dsource8
PM_MRK_DATA_FROM_RL2L3_MOD_CYC_GRP235 Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node) 3 Group 235 pm_mrk_dsource8
PM_RUN_INST_CMPL_GRP235 Number of run instructions completed. 4 Group 235 pm_mrk_dsource8
PM_RUN_CYC_GRP235 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 235 pm_mrk_dsource8
PM_INST_CMPL_GRP236 Number of PowerPC Instructions that completed. 0 Group 236 pm_mrk_dsource9
PM_MRK_DATA_FROM_DL2L3_SHR_CYC_GRP236 Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S) 1 Group 236 pm_mrk_dsource9
PM_MRK_DATA_FROM_DL2L3_SHR_GRP236 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load. 2 Group 236 pm_mrk_dsource9
PM_MRK_DATA_FROM_L2MISS_GRP236 DL1 was reloaded from beyond L2 due to a marked demand load. 3 Group 236 pm_mrk_dsource9
PM_RUN_INST_CMPL_GRP236 Number of run instructions completed. 4 Group 236 pm_mrk_dsource9
PM_RUN_CYC_GRP236 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 236 pm_mrk_dsource9
PM_MRK_DATA_FROM_RL2L3_SHR_GRP237 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load 0 Group 237 pm_mrk_dsource10
PM_MRK_DATA_FROM_RL2L3_SHR_CYC_GRP237 Marked load latency Data Source 1000 (Remote L2.5/L3.5 S) 1 Group 237 pm_mrk_dsource10
PM_DATA_FROM_RMEM_GRP237 The processor's Data Cache was reloaded from memory attached to a different module than this processor is located on. 2 Group 237 pm_mrk_dsource10
PM_INST_CMPL_GRP237 Number of PowerPC Instructions that completed. 3 Group 237 pm_mrk_dsource10
PM_RUN_INST_CMPL_GRP237 Number of run instructions completed. 4 Group 237 pm_mrk_dsource10
PM_RUN_CYC_GRP237 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 237 pm_mrk_dsource10
PM_MRK_LD_MISS_EXPOSED_CYC_GRP238 Marked Load exposed Miss 0 Group 238 pm_mrk_dsource11
PM_INST_CMPL_GRP238 Number of PowerPC Instructions that completed. 1 Group 238 pm_mrk_dsource11
PM_MRK_DATA_FROM_RMEM_GRP238 The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this processor is located on. 2 Group 238 pm_mrk_dsource11
PM_MRK_DATA_FROM_RMEM_CYC_GRP238 Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. 3 Group 238 pm_mrk_dsource11
PM_RUN_INST_CMPL_GRP238 Number of run instructions completed. 4 Group 238 pm_mrk_dsource11
PM_RUN_CYC_GRP238 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 238 pm_mrk_dsource11
PM_MRK_DATA_FROM_L31_SHR_GRP239 Marked data loaded from another L3 on same chip shared 0 Group 239 pm_mrk_dsource12
PM_MRK_DATA_FROM_L31_SHR_CYC_GRP239 Marked load latency Data source 0110 (L3.1 S) 1 Group 239 pm_mrk_dsource12
PM_MRK_INST_FIN_GRP239 One of the execution units finished a marked instruction. Instructions that finish may not necessary complete 2 Group 239 pm_mrk_dsource12
PM_INST_CMPL_GRP239 Number of PowerPC Instructions that completed. 3 Group 239 pm_mrk_dsource12
PM_RUN_INST_CMPL_GRP239 Number of run instructions completed. 4 Group 239 pm_mrk_dsource12
PM_RUN_CYC_GRP239 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 239 pm_mrk_dsource12
PM_MRK_LD_MISS_EXPOSED_CYC_COUNT_GRP240 Marked Load exposed Miss (use edge detect to count #) 0 Group 240 pm_mrk_dsource13
PM_INST_CMPL_GRP240 Number of PowerPC Instructions that completed. 1 Group 240 pm_mrk_dsource13
PM_MRK_DATA_FROM_DL2L3_MOD_GRP240 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load. 2 Group 240 pm_mrk_dsource13
PM_MRK_DATA_FROM_DL2L3_MOD_CYC_GRP240 Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node) 3 Group 240 pm_mrk_dsource13
PM_RUN_INST_CMPL_GRP240 Number of run instructions completed. 4 Group 240 pm_mrk_dsource13
PM_RUN_CYC_GRP240 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 240 pm_mrk_dsource13
PM_MRK_LSU_FLUSH_ULD_GRP241 A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) 0 Group 241 pm_mrk_lsu_flush1
PM_MRK_LSU_FLUSH_UST_GRP241 A marked store was flushed because it was unaligned 1 Group 241 pm_mrk_lsu_flush1
PM_INST_CMPL_GRP241 Number of PowerPC Instructions that completed. 2 Group 241 pm_mrk_lsu_flush1
PM_CYC_GRP241 Processor Cycles 3 Group 241 pm_mrk_lsu_flush1
PM_RUN_INST_CMPL_GRP241 Number of run instructions completed. 4 Group 241 pm_mrk_lsu_flush1
PM_RUN_CYC_GRP241 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 241 pm_mrk_lsu_flush1
PM_INST_CMPL_GRP242 Number of PowerPC Instructions that completed. 0 Group 242 pm_mrk_lsu_flush2
PM_CYC_GRP242 Processor Cycles 1 Group 242 pm_mrk_lsu_flush2
PM_MRK_LSU_FLUSH_LRQ_GRP242 Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. 2 Group 242 pm_mrk_lsu_flush2
PM_MRK_LSU_FLUSH_SRQ_GRP242 Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. 3 Group 242 pm_mrk_lsu_flush2
PM_RUN_INST_CMPL_GRP242 Number of run instructions completed. 4 Group 242 pm_mrk_lsu_flush2
PM_RUN_CYC_GRP242 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 242 pm_mrk_lsu_flush2
PM_MRK_LSU_REJECT_LHS_GRP243 The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully 0 Group 243 pm_mrk_rejects
PM_MRK_LSU_FLUSH_GRP243 Marked flush initiated by LSU 1 Group 243 pm_mrk_rejects
PM_INST_CMPL_GRP243 Number of PowerPC Instructions that completed. 2 Group 243 pm_mrk_rejects
PM_MRK_LSU_REJECT_GRP243 LSU marked reject (up to 2 per cycle) 3 Group 243 pm_mrk_rejects
PM_RUN_INST_CMPL_GRP243 Number of run instructions completed. 4 Group 243 pm_mrk_rejects
PM_RUN_CYC_GRP243 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 243 pm_mrk_rejects
PM_MRK_INST_ISSUED_GRP244 A marked instruction was issued to an execution unit. 0 Group 244 pm_mrk_inst
PM_MRK_INST_DISP_GRP244 A marked instruction was dispatched 1 Group 244 pm_mrk_inst
PM_MRK_INST_FIN_GRP244 One of the execution units finished a marked instruction. Instructions that finish may not necessary complete 2 Group 244 pm_mrk_inst
PM_INST_CMPL_GRP244 Number of PowerPC Instructions that completed. 3 Group 244 pm_mrk_inst
PM_RUN_INST_CMPL_GRP244 Number of run instructions completed. 4 Group 244 pm_mrk_inst
PM_RUN_CYC_GRP244 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 244 pm_mrk_inst
PM_MRK_ST_CMPL_GRP245 A sampled store has completed (data home) 0 Group 245 pm_mrk_st
PM_MRK_ST_NEST_GRP245 A sampled store has been sent to the memory subsystem 1 Group 245 pm_mrk_st
PM_MRK_ST_CMPL_INT_GRP245 A marked store previously sent to the memory subsystem completed (data home) after requiring intervention 2 Group 245 pm_mrk_st
PM_INST_CMPL_GRP245 Number of PowerPC Instructions that completed. 3 Group 245 pm_mrk_st
PM_RUN_INST_CMPL_GRP245 Number of run instructions completed. 4 Group 245 pm_mrk_st
PM_RUN_CYC_GRP245 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 245 pm_mrk_st
PM_INST_CMPL_GRP246 Number of PowerPC Instructions that completed. 0 Group 246 pm_mrk_dtlb_miss1
PM_MRK_DTLB_MISS_4K_GRP246 Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. 1 Group 246 pm_mrk_dtlb_miss1
PM_MRK_DTLB_MISS_64K_GRP246 Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. 2 Group 246 pm_mrk_dtlb_miss1
PM_MRK_DTLB_MISS_16M_GRP246 Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. 3 Group 246 pm_mrk_dtlb_miss1
PM_RUN_INST_CMPL_GRP246 Number of run instructions completed. 4 Group 246 pm_mrk_dtlb_miss1
PM_RUN_CYC_GRP246 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 246 pm_mrk_dtlb_miss1
PM_MRK_DTLB_MISS_16G_GRP247 Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. 0 Group 247 pm_mrk_dtlb_miss2
PM_MRK_DTLB_MISS_4K_GRP247 Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. 1 Group 247 pm_mrk_dtlb_miss2
PM_MRK_DTLB_MISS_64K_GRP247 Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. 2 Group 247 pm_mrk_dtlb_miss2
PM_INST_CMPL_GRP247 Number of PowerPC Instructions that completed. 3 Group 247 pm_mrk_dtlb_miss2
PM_RUN_INST_CMPL_GRP247 Number of run instructions completed. 4 Group 247 pm_mrk_dtlb_miss2
PM_RUN_CYC_GRP247 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 247 pm_mrk_dtlb_miss2
PM_INST_CMPL_GRP248 Number of PowerPC Instructions that completed. 0 Group 248 pm_mrk_derat_miss1
PM_MRK_DERAT_MISS_64K_GRP248 A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. 1 Group 248 pm_mrk_derat_miss1
PM_MRK_DERAT_MISS_16M_GRP248 A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. 2 Group 248 pm_mrk_derat_miss1
PM_MRK_DERAT_MISS_16G_GRP248 A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload. 3 Group 248 pm_mrk_derat_miss1
PM_RUN_INST_CMPL_GRP248 Number of run instructions completed. 4 Group 248 pm_mrk_derat_miss1
PM_RUN_CYC_GRP248 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 248 pm_mrk_derat_miss1
PM_MRK_DERAT_MISS_4K_GRP249 A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload. 0 Group 249 pm_mrk_derat_miss2
PM_MRK_DERAT_MISS_64K_GRP249 A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. 1 Group 249 pm_mrk_derat_miss2
PM_MRK_DERAT_MISS_16M_GRP249 A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. 2 Group 249 pm_mrk_derat_miss2
PM_INST_CMPL_GRP249 Number of PowerPC Instructions that completed. 3 Group 249 pm_mrk_derat_miss2
PM_RUN_INST_CMPL_GRP249 Number of run instructions completed. 4 Group 249 pm_mrk_derat_miss2
PM_RUN_CYC_GRP249 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 249 pm_mrk_derat_miss2
PM_MRK_LD_MISS_EXPOSED_CYC_GRP250 Marked Load exposed Miss 0 Group 250 pm_mrk_misc_miss
PM_INST_CMPL_GRP250 Number of PowerPC Instructions that completed. 1 Group 250 pm_mrk_misc_miss
PM_MRK_LSU_DERAT_MISS_GRP250 Marked DERAT Miss 2 Group 250 pm_mrk_misc_miss
PM_MRK_LD_MISS_L1_CYC_GRP250 L1 data load miss cycles 3 Group 250 pm_mrk_misc_miss
PM_RUN_INST_CMPL_GRP250 Number of run instructions completed. 4 Group 250 pm_mrk_misc_miss
PM_RUN_CYC_GRP250 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 250 pm_mrk_misc_miss
PM_INST_CMPL_GRP251 Number of PowerPC Instructions that completed. 0 Group 251 pm_mrk_pteg1
PM_MRK_PTEG_FROM_DMEM_GRP251 A Page Table Entry was loaded into the ERAT from memory attached to a different module than this processor is located on due to a marked load or store. 1 Group 251 pm_mrk_pteg1
PM_MRK_PTEG_FROM_L21_MOD_GRP251 Marked PTEG loaded from another L2 on same chip modified 2 Group 251 pm_mrk_pteg1
PM_MRK_PTEG_FROM_L21_SHR_GRP251 Marked PTEG loaded from another L2 on same chip shared 3 Group 251 pm_mrk_pteg1
PM_RUN_INST_CMPL_GRP251 Number of run instructions completed. 4 Group 251 pm_mrk_pteg1
PM_RUN_CYC_GRP251 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 251 pm_mrk_pteg1
PM_MRK_PTEG_FROM_L2_GRP252 A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store. 0 Group 252 pm_mrk_pteg2
PM_MRK_PTEG_FROM_RL2L3_SHR_GRP252 A Page Table Entry was loaded into the ERAT from memory attached to a different module than this processor is located on due to a marked load or store. 1 Group 252 pm_mrk_pteg2
PM_MRK_PTEG_FROM_RMEM_GRP252 A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB 2 Group 252 pm_mrk_pteg2
PM_INST_CMPL_GRP252 Number of PowerPC Instructions that completed. 3 Group 252 pm_mrk_pteg2
PM_RUN_INST_CMPL_GRP252 Number of run instructions completed. 4 Group 252 pm_mrk_pteg2
PM_RUN_CYC_GRP252 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 252 pm_mrk_pteg2
PM_INST_CMPL_GRP253 Number of PowerPC Instructions that completed. 0 Group 253 pm_mrk_pteg3
PM_MRK_PTEG_FROM_L31_SHR_GRP253 Marked PTEG loaded from another L3 on same chip shared 1 Group 253 pm_mrk_pteg3
PM_MRK_PTEG_FROM_L21_MOD_GRP253 Marked PTEG loaded from another L2 on same chip modified 2 Group 253 pm_mrk_pteg3
PM_MRK_PTEG_FROM_DL2L3_MOD_GRP253 A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a marked load or store. 3 Group 253 pm_mrk_pteg3
PM_RUN_INST_CMPL_GRP253 Number of run instructions completed. 4 Group 253 pm_mrk_pteg3
PM_RUN_CYC_GRP253 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 253 pm_mrk_pteg3
PM_MRK_PTEG_FROM_L31_MOD_GRP254 Marked PTEG loaded from another L3 on same chip modified 0 Group 254 pm_mrk_pteg4
PM_MRK_PTEG_FROM_L3_GRP254 A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store. 1 Group 254 pm_mrk_pteg4
PM_INST_CMPL_GRP254 Number of PowerPC Instructions that completed. 2 Group 254 pm_mrk_pteg4
PM_MRK_PTEG_FROM_L2MISS_GRP254 A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store. 3 Group 254 pm_mrk_pteg4
PM_RUN_INST_CMPL_GRP254 Number of run instructions completed. 4 Group 254 pm_mrk_pteg4
PM_RUN_CYC_GRP254 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 254 pm_mrk_pteg4
PM_MRK_PTEG_FROM_RL2L3_MOD_GRP255 A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store. 0 Group 255 pm_mrk_pteg5
PM_MRK_PTEG_FROM_L3MISS_GRP255 A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store 1 Group 255 pm_mrk_pteg5
PM_INST_CMPL_GRP255 Number of PowerPC Instructions that completed. 2 Group 255 pm_mrk_pteg5
PM_MRK_PTEG_FROM_LMEM_GRP255 A Page Table Entry was loaded into the ERAT from memory attached to the same module this processor is located on due to a marked load or store. 3 Group 255 pm_mrk_pteg5
PM_RUN_INST_CMPL_GRP255 Number of run instructions completed. 4 Group 255 pm_mrk_pteg5
PM_RUN_CYC_GRP255 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 255 pm_mrk_pteg5
PM_MRK_STCX_FAIL_GRP256 A marked stcx (stwcx or stdcx) failed 0 Group 256 pm_mrk_misc1
PM_INST_CMPL_GRP256 Number of PowerPC Instructions that completed. 1 Group 256 pm_mrk_misc1
PM_MRK_IFU_FIN_GRP256 The Instruction Fetch Unit finished a marked instruction. 2 Group 256 pm_mrk_misc1
PM_MRK_INST_TIMEO_GRP256 The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed. 3 Group 256 pm_mrk_misc1
PM_RUN_INST_CMPL_GRP256 Number of run instructions completed. 4 Group 256 pm_mrk_misc1
PM_RUN_CYC_GRP256 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 256 pm_mrk_misc1
PM_INST_CMPL_GRP257 Number of PowerPC Instructions that completed. 0 Group 257 pm_mrk_misc2
PM_MRK_FXU_FIN_GRP257 One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete. 1 Group 257 pm_mrk_misc2
PM_MRK_IFU_FIN_GRP257 The Instruction Fetch Unit finished a marked instruction. 2 Group 257 pm_mrk_misc2
PM_MRK_LSU_FIN_GRP257 One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete 3 Group 257 pm_mrk_misc2
PM_RUN_INST_CMPL_GRP257 Number of run instructions completed. 4 Group 257 pm_mrk_misc2
PM_RUN_CYC_GRP257 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 257 pm_mrk_misc2
PM_INST_CMPL_GRP258 Number of PowerPC Instructions that completed. 0 Group 258 pm_mrk_misc3
PM_MRK_BRU_FIN_GRP258 The branch unit finished a marked instruction. Instructions that finish may not necessary complete. 1 Group 258 pm_mrk_misc3
PM_MRK_LSU_PARTIAL_CDF_GRP258 A partial cacheline was returned from the L3 for a marked load 2 Group 258 pm_mrk_misc3
PM_MRK_LSU_FIN_GRP258 One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete 3 Group 258 pm_mrk_misc3
PM_RUN_INST_CMPL_GRP258 Number of run instructions completed. 4 Group 258 pm_mrk_misc3
PM_RUN_CYC_GRP258 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 258 pm_mrk_misc3
PM_MRK_FIN_STALL_CYC_GRP259 Marked instruction Finish Stall cycles (marked finish after NTC) 0 Group 259 pm_mrk_misc4
PM_INST_CMPL_GRP259 Number of PowerPC Instructions that completed. 1 Group 259 pm_mrk_misc4
PM_MRK_VSU_FIN_GRP259 vsu (fpu) marked instr finish 2 Group 259 pm_mrk_misc4
PM_MRK_GRP_IC_MISS_GRP259 A group containing a marked (sampled) instruction experienced an instruction cache miss. 3 Group 259 pm_mrk_misc4
PM_RUN_INST_CMPL_GRP259 Number of run instructions completed. 4 Group 259 pm_mrk_misc4
PM_RUN_CYC_GRP259 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 259 pm_mrk_misc4
PM_MRK_FIN_STALL_CYC_COUNT_GRP260 Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #) 0 Group 260 pm_mrk_misc5
PM_MRK_DFU_FIN_GRP260 The Decimal Floating Point Unit finished a marked instruction. 1 Group 260 pm_mrk_misc5
PM_MRK_STALL_CMPLU_CYC_COUNT_GRP260 Marked Group Completion Stall cycles (use edge detect to count #) 2 Group 260 pm_mrk_misc5
PM_INST_CMPL_GRP260 Number of PowerPC Instructions that completed. 3 Group 260 pm_mrk_misc5
PM_RUN_INST_CMPL_GRP260 Number of run instructions completed. 4 Group 260 pm_mrk_misc5
PM_RUN_CYC_GRP260 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 260 pm_mrk_misc5
PM_GRP_MRK_CYC_GRP261 cycles IDU marked instruction before dispatch 0 Group 261 pm_mrk_misc6
PM_RUN_CYC_GRP261 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 1 Group 261 pm_mrk_misc6
PM_INST_CMPL_GRP261 Number of PowerPC Instructions that completed. 2 Group 261 pm_mrk_misc6
PM_MRK_GRP_CMPL_GRP261 A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group. 3 Group 261 pm_mrk_misc6
PM_RUN_INST_CMPL_GRP261 Number of run instructions completed. 4 Group 261 pm_mrk_misc6
PM_RUN_CYC_GRP261 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 261 pm_mrk_misc6
PM_MRK_LSU_REJECT_LHS_GRP262 The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully 0 Group 262 pm_mrk_misc7
PM_INST_CMPL_GRP262 Number of PowerPC Instructions that completed. 1 Group 262 pm_mrk_misc7
PM_MRK_LSU_REJECT_ERAT_MISS_GRP262 LSU marked reject due to ERAT (up to 2 per cycle) 2 Group 262 pm_mrk_misc7
PM_MRK_LSU_REJECT_GRP262 LSU marked reject (up to 2 per cycle) 3 Group 262 pm_mrk_misc7
PM_RUN_INST_CMPL_GRP262 Number of run instructions completed. 4 Group 262 pm_mrk_misc7
PM_RUN_CYC_GRP262 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 262 pm_mrk_misc7
PM_CYC_GRP263 Processor Cycles 0 Group 263 pm_mrk_misc8
PM_CYC_GRP263 Processor Cycles 1 Group 263 pm_mrk_misc8
PM_INST_CMPL_GRP263 Number of PowerPC Instructions that completed. 2 Group 263 pm_mrk_misc8
PM_MRK_LSU_FIN_GRP263 One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete 3 Group 263 pm_mrk_misc8
PM_RUN_INST_CMPL_GRP263 Number of run instructions completed. 4 Group 263 pm_mrk_misc8
PM_RUN_CYC_GRP263 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 263 pm_mrk_misc8
PM_GCT_NOSLOT_CYC_EDGE_COUNT_GRP264 Number of distinct occurrences when the Global Completion Table has no slots from this thread. 0 Group 264 pm_gct_noslot
PM_GCT_EMPTY_CYC_GRP264 Cycles when the Global Completion Table was completely empty. No thread had an entry allocated. 1 Group 264 pm_gct_noslot
PM_INST_CMPL_GRP264 Number of PowerPC Instructions that completed. 2 Group 264 pm_gct_noslot
PM_GCT_NOSLOT_BR_MPRED_EDGE_COUNT_GRP264 Number of distinct occurrences when the Global Completion Table has no slots from this thread because of a branch misprediction. 3 Group 264 pm_gct_noslot
PM_RUN_INST_CMPL_GRP264 Number of run instructions completed. 4 Group 264 pm_gct_noslot
PM_RUN_CYC_GRP264 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 264 pm_gct_noslot
PM_CMPLU_STALL_THRD_EDGE_COUNT_GRP265 Number of distinct occurrences when completion stalled due to thread conflict. Group ready to complete but it was another thread's turn 0 Group 265 pm_cmplu_stall
PM_CMPLU_STALL_DFU_GRP265 Completion stall caused by Decimal Floating Point Unit 1 Group 265 pm_cmplu_stall
PM_INST_CMPL_GRP265 Number of PowerPC Instructions that completed. 2 Group 265 pm_cmplu_stall
PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP265 No slot in GCT caused by branch mispredict or I cache miss 3 Group 265 pm_cmplu_stall
PM_RUN_INST_CMPL_GRP265 Number of run instructions completed. 4 Group 265 pm_cmplu_stall
PM_RUN_CYC_GRP265 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 265 pm_cmplu_stall
PM_CMPLU_STALL_END_GCT_NOSLOT_GRP266 Count ended because GCT went empty 0 Group 266 pm_cmplu_stall2
PM_CMPLU_STALL_VECTOR_EDGE_COUNT_GRP266 Number of distinct occurrences when completion stalled caused by Vector instruction 1 Group 266 pm_cmplu_stall2
PM_MRK_STALL_CMPLU_CYC_COUNT_GRP266 Marked Group Completion Stall cycles (use edge detect to count #) 2 Group 266 pm_cmplu_stall2
PM_CMPLU_STALL_EDGE_COUNT_GRP266 Number of distinct occurrences when no groups completed, GCT not empty 3 Group 266 pm_cmplu_stall2
PM_RUN_INST_CMPL_GRP266 Number of run instructions completed. 4 Group 266 pm_cmplu_stall2
PM_RUN_CYC_GRP266 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 266 pm_cmplu_stall2
PM_FLOP_GRP267 A floating point operation has completed 0 Group 267 pm_cmplu_stall3
PM_CMPLU_STALL_SCALAR_LONG_GRP267 Completion stall caused by long latency scalar instruction 1 Group 267 pm_cmplu_stall3
PM_MRK_STALL_CMPLU_CYC_GRP267 Marked Group Completion Stall cycles 2 Group 267 pm_cmplu_stall3
PM_CMPLU_STALL_SCALAR_EDGE_COUNT_GRP267 Number of distinct occurrences when completion stalled caused by FPU instruction 3 Group 267 pm_cmplu_stall3
PM_RUN_INST_CMPL_GRP267 Number of run instructions completed. 4 Group 267 pm_cmplu_stall3
PM_RUN_CYC_GRP267 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 267 pm_cmplu_stall3
PM_CMPLU_STALL_END_GCT_NOSLOT_GRP268 Count ended because GCT went empty 0 Group 268 pm_cmplu_ifu
PM_LSU0_L1_SW_PREF_GRP268 LSU0 Software L1 Prefetches, including SW Transient Prefetches 1 Group 268 pm_cmplu_ifu
PM_LSU1_L1_SW_PREF_GRP268 LSU1 Software L1 Prefetches, including SW Transient Prefetches 2 Group 268 pm_cmplu_ifu
PM_CMPLU_STALL_IFU_EDGE_COUNT_GRP268 Number of distinct occurrences when completion stalled due to IFU 3 Group 268 pm_cmplu_ifu
PM_RUN_INST_CMPL_GRP268 Number of run instructions completed. 4 Group 268 pm_cmplu_ifu
PM_RUN_CYC_GRP268 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. 5 Group 268 pm_cmplu_ifu
Don't speculate - benchmark. - Dan Bernstein
2014/09/12