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ppc64 POWER8 events

This is a list of all ppc64 POWER8's performance counter event types.

NameDescriptionCounters usable
CYCLES Cycles 0
PM_1PLUS_PPC_CMPL one or more ppc instructions finished 0
PM_1PLUS_PPC_DISP Cycles at least one Instr Dispatched 3
PM_ANY_THRD_RUN_CYC One of threads in run_cycles 0
PM_BR_MPRED_CMPL Number of Branch Mispredicts 3
PM_BR_TAKEN_CMPL New event for Branch Taken 1
PM_CYC Cycles 0
PM_DATA_FROM_L2MISS Demand LD - L2 Miss (not L2 hit) 1
PM_DATA_FROM_L3MISS Demand LD - L3 Miss (not L2 hit and not L3 hit) 2
PM_DATA_FROM_MEM data from Memory 3
PM_DTLB_MISS Data PTEG reload 2
PM_EXT_INT external interrupt 1
PM_FLOP Floating Point Operations Finished 0
PM_FLUSH Flush (any type) 3
PM_GCT_NOSLOT_CYC No itags assigned 0
PM_IERAT_MISS Cycles Instruction ERAT was reloaded 0
PM_INST_DISP Number of PPC Dispatched 1
PM_INST_FROM_L3MISS 2
PM_ITLB_MISS ITLB Reloaded (always zero on POWER6) 3
PM_L1_DCACHE_RELOAD_VALID DL1 reloaded due to Demand Load 2
PM_L1_ICACHE_MISS Demand iCache Miss 1
PM_LD_MISS_L1 Load Missed L1 3
PM_LSU_DERAT_MISS DERAT Reloaded due to a DERAT miss 1
PM_MRK_BR_MPRED_CMPL Marked Branch Mispredicted 2
PM_MRK_BR_TAKEN_CMPL Marked Branch Taken completed 0
PM_MRK_DATA_FROM_L2MISS sampled load resolved beyond L2 3
PM_MRK_DATA_FROM_L3MISS sampled load resolved beyond L3 1
PM_MRK_DATA_FROM_MEM sampled load resolved from memory 1
PM_MRK_DERAT_MISS Erat Miss (TLB Access) All page sizes 2
PM_MRK_DTLB_MISS sampled Instruction dtlb miss 3
PM_MRK_INST_CMPL Marked group complete 3
PM_MRK_INST_DISP The thread has dispatched a randomly sampled marked instruction 0
PM_MRK_INST_FROM_L3MISS cache 3
PM_MRK_L1_ICACHE_MISS sampled Instruction suffered an icache Miss 0
PM_MRK_L1_RELOAD_VALID Sampled Instruction had a data reload 0
PM_MRK_LD_MISS_L1 Marked DL1 Demand Miss 1
PM_MRK_ST_CMPL marked store completed and sent to nest 2
PM_RUN_CYC Run_cycles 5
PM_RUN_INST_CMPL Run_Instructions 4
PM_RUN_PURR Run_PURR 3
PM_ST_FIN Store Instructions Finished 1
PM_ST_MISS_L1 Store Missed L1 2
PM_TB_BIT_TRANS timebase event 2
PM_THRD_CONC_RUN_INST PPC Instructions Finished when both threads in run_cycles 2
PM_THRESH_EXC_1024 increments when the threshold exceeded a count of 1024 2
PM_THRESH_EXC_128 count of 128 3
PM_THRESH_EXC_2048 count of 2048 3
PM_THRESH_EXC_256 count of 256 0
PM_THRESH_EXC_32 count of 32 1
PM_THRESH_EXC_4096 count of 4096 0
PM_THRESH_EXC_512 increments when the threshold exceeded a count of 512 1
PM_THRESH_EXC_64 increments when the threshold exceeded a count of 64 2
PM_THRESH_MET Threshold exceeded 0
PM_BR_2PATH two path branch. 3
PM_BR_CMPL Branch Instruction completed. 3
PM_BR_MRK_2PATH marked two path branch. 3
PM_CMPLU_STALL Completion stall. 0
PM_CMPLU_STALL_BRU Completion stall due to a Branch Unit. 3
PM_CMPLU_STALL_BRU_CRU Completion stall due to IFU. 1
PM_CMPLU_STALL_COQ_FULL Completion stall due to CO q full. 2
PM_CMPLU_STALL_DCACHE_MISS Completion stall by Dcache miss. 1
PM_CMPLU_STALL_DMISS_L21_L31 Completion stall by Dcache miss. 1
PM_CMPLU_STALL_DMISS_L2L3 Completion stall by Dcache miss which resolved in L2/L3. 1
PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 3
PM_CMPLU_STALL_DMISS_L3MISS Completion stall due to cache miss resolving missed the L3. 3
PM_CMPLU_STALL_DMISS_LMEM Completion stall due to cache miss resolving in core's Local Memory. 3
PM_CMPLU_STALL_DMISS_REMOTE Completion stall due to cache miss resolving in core's Local Memory. 1
PM_CMPLU_STALL_ERAT_MISS Completion stall due to LSU reject ERAT miss. 3
PM_CMPLU_STALL_FLUSH completion stall due to flush by own thread. 2
PM_CMPLU_STALL_FXLONG Completion stall due to a long latency fixed point instruction. 3
PM_CMPLU_STALL_FXU Completion stall due to FXU. 1
PM_CMPLU_STALL_HWSYNC completion stall due to hwsync. 2
PM_CMPLU_STALL_LOAD_FINISH Completion stall due to a Load finish. 3
PM_CMPLU_STALL_LSU Completion stall by LSU instruction. 1
PM_CMPLU_STALL_LWSYNC completion stall due to isync/lwsync. 0
PM_CMPLU_STALL_MEM_ECC_DELAY Completion stall due to mem ECC delay. 2
PM_CMPLU_STALL_NTCG_FLUSH Completion stall due to reject (load hit store). 1
PM_CMPLU_STALL_OTHER_CMPL Instructions core completed while this thread was stalled. 2
PM_CMPLU_STALL_REJECT Completion stall due to LSU reject. 3
PM_CMPLU_STALL_REJECT_LHS Completion stall due to reject (load hit store). 1
PM_CMPLU_STALL_REJ_LMQ_FULL Completion stall due to LSU reject LMQ full. 3
PM_CMPLU_STALL_SCALAR Completion stall due to VSU scalar instruction. 3
PM_CMPLU_STALL_SCALAR_LONG Completion stall due to VSU scalar long latency instruction. 1
PM_CMPLU_STALL_STORE Completion stall by stores. 1
PM_CMPLU_STALL_ST_FWD Completion stall due to store forward. 3
PM_CMPLU_STALL_THRD Completion stall due to thread conflict. 0
PM_CMPLU_STALL_VECTOR Completion stall due to VSU vector instruction. 1
PM_CMPLU_STALL_VECTOR_LONG Completion stall due to VSU vector long instruction. 3
PM_CMPLU_STALL_VSU Completion stall due to VSU instruction. 1
PM_DATA_FROM_L2 load plus prefetch controlled by MMCR1[20]. 0
PM_DATA_FROM_L2_NO_CONFLICT demand load or demand load plus prefetch controlled by MMCR1[20] . 0
PM_DATA_FROM_L3 demand load or demand load plus prefetch controlled by MMCR1[20] . 3
PM_DATA_FROM_L3MISS_MOD to a demand load. 3
PM_DATA_FROM_L3_NO_CONFLICT demand load or demand load plus prefetch controlled by MMCR1[20]. 0
PM_DATA_FROM_LMEM 1
PM_DATA_FROM_MEMORY remote or distant due to a demand load. 1
PM_DC_PREF_STREAM_STRIDED_CONF 2
PM_GCT_NOSLOT_BR_MPRED Gct empty fo this thread due to branch mispred. 3
PM_GCT_NOSLOT_BR_MPRED_ICMISS Gct empty fo this thread due to Icache Miss and branch mispred. 3
PM_GCT_NOSLOT_DISP_HELD_ISSQ Gct empty fo this thread due to Icache Miss and branch mispred. 1
PM_GCT_NOSLOT_DISP_HELD_OTHER 1
PM_GCT_NOSLOT_DISP_HELD_SRQ 1
PM_GCT_NOSLOT_IC_L3MISS Gct empty fo this thread due to icach l3 miss. 3
PM_GCT_NOSLOT_IC_MISS Gct empty fo this thread due to Icache Miss. 1
PM_GRP_DISP. 2 dispatch_success Group Dispatched
PM_GRP_MRK Instruction marked in idu. 0
PM_HV_CYC cycles in hypervisor mode . 1
PM_INST_CMPL PPC Instructions Finished (completed). 0
PM_IOPS_CMPL IOPS Completed. 0
PM_LD_CMPL count of Loads completed. 0
PM_LD_L3MISS_PEND_CYC Cycles L3 miss was pending for this thread. 0
PM_MRK_DATA_FROM_L2 Cycles L3 miss was pending for this thread. 0
PM_MRK_DATA_FROM_L2MISS_CYC marked load. 3
PM_MRK_DATA_FROM_L2_CYC Duration in cycles to reload from local core's L2 due to a marked load. 3
PM_MRK_DATA_FROM_L2_NO_CONFLICT marked load. 0
PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 3
PM_MRK_DATA_FROM_L3 3
PM_MRK_DATA_FROM_L3MISS_CYC marked load. 1
PM_MRK_DATA_FROM_L3_CYC Duration in cycles to reload from local core's L3 due to a marked load. 1
PM_MRK_DATA_FROM_L3_NO_CONFLICT marked load. 0
PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 3
PM_MRK_DATA_FROM_LL4 load. 0
PM_MRK_DATA_FROM_LL4_CYC load. 3
PM_MRK_DATA_FROM_LMEM 1
PM_MRK_DATA_FROM_LMEM_CYC 3
PM_MRK_DATA_FROM_MEMORY remote or distant due to a marked load. 1
PM_MRK_DATA_FROM_MEMORY_CYC distant due to a marked load. 3
PM_MRK_GRP_CMPL marked instruction finished (completed). 3
PM_MRK_INST_DECODED marked instruction decoded. Name from ISU? 1
PM_MRK_L2_RC_DISP Marked Instruction RC dispatched in L2. 1
PM_MRK_LD_MISS_L1_CYC Marked ld latency. 3
PM_MRK_STALL_CMPLU_CYC Marked Group Completion Stall cycles (use edge detect to count ). 2
PM_NEST_REF_CLK Nest reference clocks. 2
PM_PMC1_OVERFLOW Overflow from counter 1. 1
PM_PMC2_OVERFLOW Overflow from counter 2. 2
PM_PMC3_OVERFLOW Overflow from counter 3. 3
PM_PMC4_OVERFLOW Overflow from counter 4. 0
PM_PMC6_OVERFLOW Overflow from counter 6. 2
PM_PPC_CMPL PPC Instructions Finished (completed). 3
PM_THRD_ALL_RUN_CYC All Threads in Run_cycles (was both threads in run_cycles). 1
PM_THRESH_NOT_MET Threshold counter did not meet threshold. 3
A wise man proportions his belief to the evidence. - David Hume
2013/07/29