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Tilera tile64 events

This is a list of all tile64 CPU's performance counter event types. Please see Tilera development doc: Multicore Development Environment Optimization Guide. Contact Tilera Corporation or visit http://www.tilera.com for more information.

NameDescriptionCounters usableUnit mask options
ZERO Always zero - no event ever happens all
ONE Always one - an event occurs every cycle all
PASS_WRITTEN The event indicates that the PASS SPR was written all
FAIL_WRITTEN The event indicates that the FAIL SPR was written all
DONE_WRITTEN The event indicates that the DONE SPR was written all
MP_BUNDLE_RETIRED The event occurs when instruction bundle is retired. all
MP_UDN_READ_STALL An event occurs every cycle that an instruction bundle is stalled on a UDN read. Multiple stall events may occur and be counted during the same cycle. This behavior is errata for TILE64 because the event is actually triggered only once per instruction stall rather than once per cycle of an instruction stall. all
MP_IDN_READ_STALL An event occurs every cycle that an instruction bundle is stalled on a IDN read. Multiple stall events may occur and be counted during the same cycle. This behavior is errata for TILE64 because the event is actually triggered only once per instruction stall rather than once per cycle of an instruction stall. all
MP_SN_READ_STALL An event occurs every cycle that an instruction bundle is stalled on a STN read. Multiple stall events may occur and be counted during the same cycle. This behavior is errata for TILE64 because the event is actually triggered only once per instruction stall rather than once per cycle of an instruction stall. all
MP_UDN_WRITE_STALL An event occurs every cycle that an instruction bundle is stalled on a UDN write. Multiple stall events may occur and be counted during the same cycle. all
MP_IDN_WRITE_STALL An event occurs every cycle that an instruction bundle is stalled on a IDN write. Multiple stall events may occur and be counted during the same cycle. all
MP_SN_WRITE_STALL An event occurs every cycle that an instruction bundle is stalled on a STN write. Multiple stall events may occur and be counted during the same cycle. all
MP_DATA_CACHE_STALL An event occurs every cycle that an instruction bundle is stalled on a data memory operation except for the cycles when a replay trap is being performed. Instructions that depend on the result of a load and are fired speculatively cause a reply trap if the request misses the L1 data cache and thus are not counted. The wait is 4 if the consumer of the load immediately follows the load or 3 if there is a cycle between the load issue and the consumer issue. Multiple stall events may occur and be counted during the same cycle. all
MP_INSTRUCTION_CACHE_STALL An event occurs every cycle that an instruction bundle is stalled on a instruction memory operation. Multiple stall events may occur and be counted during the same cycle. all
TLB_HIT The event occurs when the address of a data stream memory operation hits in the Data TLB. It includes speculative requests down branch paths. all
TLB_EXC The event occurs when the address of a data stream memory operation causes a Data TLB Exception including TLB Misses and protection violations. all
HIT This event occurs when a load instruction hits in the L1 Data cache. all
MEM_REQ_RD The event occurs when a read or TNS request to main memory leaves the Tile. all
MEM_REQ_WR The event occurs when a write request to main memory, including explicit flushes and non-cacheable stores, leaves the Tile. all
MEM_REQ_VIC The event occurs when a cache writeback to main memory, including victim writes or explicit flushes, leaves the Tile. all
MISS_I The event occurs when an instruction stream read misses the L2 cache due to an L1 instruction cache miss. all
MISS_D_WR The event occurs when a store request misses the L2 cache with the page cached locally or remotely. all
MISS_D_RD The event occurs when a load request or instruction prefetch misses the L2 cache due to an L1 miss with the page cached locally or remotely. all
MISS_TDN This event occurs when a snoop incoming on the TDN misses the L2 cache. all
OLOC_REQ_RD This event occurs when a remote read request is sent to another Tile, including load miss, data stream prefetch miss, and instruction stream prefetch miss. all
OLOC_REQ_WR This event occurs when a remote write request is sent to another Tile, including all stores whether they hit local or don't hit and write through the L2 cache. all
L2_HIT This event occurs when any cache access hits the L2 and includes MDN fills and Memory Fence operations locally or remotely issued. all
L2_INV The event occurs when an inval, flush, or finv hits a clean L2 cache block. all
TDN_STARVED The event occurs when a snoop is received and the controller enters the TDN starved condition. all
DMA_STARVED The event occurs when a DMA is received and the controller enters the starved condition. all
MDN_STARVED The event occurs when the controller enters the MDN starved condition. all
RTF_STARVED The event occurs when the controller enters the re-try FIFO starved condition. all
IREQ_STARVED The event occurs when the controller enters the instruction stream starved condition. all
RRTF_STARVED The event occurs when the controller enters the remote re-try FIFO starved condition. all
Optimizations always bust things, because all optimizations are, in the long haul, a form of cheating, and cheaters eventually get caught. - Larry Wall
2014/09/12