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Tilera tilepro events

This is a list of all tilepro CPU's performance counter event types. Please see Tilera development doc: Multicore Development Environment Optimization Guide. Contact Tilera Corporation or visit http://www.tilera.com for more information.

NameDescriptionCounters usableUnit mask options
ZERO Always zero - no event ever happens all
ONE Always one - an event occurs every cycle all
PASS_WRITTEN The event indicates that the PASS SPR was written all
FAIL_WRITTEN The event indicates that the FAIL SPR was written all
DONE_WRITTEN The event indicates that the DONE SPR was written all
MP_BUNDLE_RETIRED The event occurs when instruction bundle is retired. all
MP_BUNDLE_1_INSTR_RETIRED The event occurs when an instruction bundle containing one valid instruction is retired. all
MP_BUNDLE_2_INSTR_RETIRED The event occurs when an instruction bundle containing two valid instructions is retired. all
MP_BUNDLE_3_INSTR_RETIRED The event occurs when an instruction bundle containing three valid instructions is retired. all
MP_UDN_READ_STALL An event occurs every cycle that an instruction bundle is stalled on a UDN read. Multiple stall events may occur and be counted during the same cycle. all
MP_IDN_READ_STALL An event occurs every cycle that an instruction bundle is stalled on a IDN read. Multiple stall events may occur and be counted during the same cycle. all
MP_SN_READ_STALL An event occurs every cycle that an instruction bundle is stalled on a STN read. Multiple stall events may occur and be counted during the same cycle. all
MP_UDN_WRITE_STALL An event occurs every cycle that an instruction bundle is stalled on a UDN write. Multiple stall events may occur and be counted during the same cycle. all
MP_IDN_WRITE_STALL An event occurs every cycle that an instruction bundle is stalled on a IDN write. Multiple stall events may occur and be counted during the same cycle. all
MP_SN_WRITE_STALL An event occurs every cycle that an instruction bundle is stalled on a STN write. Multiple stall events may occur and be counted during the same cycle. all
MP_DATA_CACHE_STALL An event occurs every cycle that an instruction bundle is stalled on a data memory operation except for the cycles when a replay trap is being performed. Instructions that depend on the result of a load and are fired speculatively cause a reply trap if the request misses the L1 data cache and thus are not counted. The wait is 4 if the consumer of the load immediately follows the load or 3 if there is a cycle between the load issue and the consumer issue. Multiple stall events may occur and be counted during the same cycle. all
MP_INSTRUCTION_CACHE_STALL An event occurs every cycle that an instruction bundle is stalled on a instruction memory operation. Multiple stall events may occur and be counted during the same cycle. all
MP_ICACHE_HIT_ISSUED The event occurs when the fetch of an issued instruction hits the L1 Instruction cache. all
MP_ITLB_HIT_ISSUED The event occurs when the fetch of an issued instruction hits the instruction TLB. all
MP_CONDITIONAL_BRANCH_MISSPREDICT The event occurs when a conditional branch is misspredicted. all
MP_INDIRECT_BRANCH_MISSPREDICT The event occurs when a register indirect branch is misspredicted. all
MP_CONDITIONAL_BRANCH_ISSUED The event occurs when a conditional branch is issued. all
MP_INDIRECT_BRANCH_ISSUED The event occurs when a register indirect branch is issued. all
MP_CACHE_BUSY_STALL The event occurs when the cache system is busy, and a memory operation cannot be issued. all
MP_NAP_STALL The event occurs every cycle a processor is stalled due to a nap instruction. all
MP_SPR_STALL The event occurs every cycle a processor is stalled when executing an instruction that reads or writes an SPR. all
MP_ALU_STALL The event occurs every cycle a processor is stalled because an operand is not available due to an arithmetic operation. For example, this event will occur when an instruction consuming the result of a multiply stall for one cycle waiting for the multiply result. all
MP_LOAD_MISS_REPLAY_TRAP The event occurs every time an instruction consuming the result of a load issues within two cycles of the load instruction, and the load instruction misses in the L1 data cache. all
TLB_CNT The event occurs when a data memory operation is issued and the data translation lookaside buffer (DTLB) is used to translate the virtual address into the physical address. all
RD_CNT The event occurs when a load is issued. all
WR_CNT The event occurs when a store is issed. all
TLB_EXCEPTION The event occurs when the address of a data stream memory operation causes a Data TLB Exception including TLB Misses and protection violations. all
RD_MISS The event occurs when a load is issued and data is not returned from the level 1 data cache. all
WR_MISS The event occurs when a store is issued and the 16-byte aligned block (level 1 data cache line size) containing the address is not present at the level 1 data cache. all
SNP_INC_RD_CNT The event occurs when a read request is received from another Tile off the TDN and the Level 3 cache will track the share state. all
SNP_NINC_RD_CNT The event occurs when a read request is received from another Tile off the TDN and the Level 3 cache will not track the share state. all
SNP_WR_CNT The event occurs when a write (store or test-and-set) request is received from another Tile off the TDN. all
SNP_IO_RD_CNT The event occurs when a read request is received from an IO device off the TDN. all
SNP_IO_WR_CNT The event occurs when a write request is received from an IO device off the TDN. all
LOCAL_DRD_CNT The event occurs when a data read request is received from the main processor and the Level 3 cache resides in the Tile. all
LOCAL_WR_CNT The event occurs when a write (store or test-and-set) request is received from the main processor and the Level 3 cache resides in the Tile. all
LOCAL_IRD_CNT The event occurs when an instruction read request is received from the main processor and the Level 3 cache resides in the Tile. all
REMOTE_DRD_CNT The event occurs when a data read request is received from the main processor and the Level 3 cache resides in another Tile. all
REMOTE_WR_CNT The event occurs when a write (store or test-and-set) request is received from the main processor and the Level 3 cache resides in another Tile. all
REMOTE_IRD_CNT The event occurs when an instruction read request is received from the main processor and the Level 3 cache resides in another Tile. all
COH_INV_CNT The event occurs when a coherence invalidation is received from another Tile off the VDN. all
SNP_INC_RD_MISS The event occurs when a read request is received from another Tile off the TDN and misses the Level 3 cache. The level 3 cache will track the share state. all
SNP_NINC_RD_MISS The event occurs when a read request is received from another Tile off the TDN and misses the Level 3 cache. The Level 3 cache will not track the share state. all
SNP_WR_MISS The event occurs when a write (store or test-and-set) request is received from another Tile off the TDN and misses the Level 3 cache. all
SNP_IO_RD_MISS The event occurs when a read request is received from an IO device off the TDN and misses the Level 3 cache. all
SNP_IO_WR_MISS The event occurs when a write request is received from an IO device off the TDN and misses the Level 3 cache. all
LOCAL_DRD_MISS The event occurs when a data read request is received from the main processor and misses the Level 3 cache resided in the Tile. all
LOCAL_WR_MISS The event occurs when a write (store or test-and-set) request is received from the main processor and misses the Level 3 cache resided in the Tile. all
LOCAL_IRD_MISS The event occurs when an instruction read request is received from the main processor and misses the Level 3 cache resided in the Tile. all
REMOTE_DRD_MISS The event occurs when a data read request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile. all
REMOTE_WR_MISS The event occurs when a write (store or test-and-set) request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile. all
REMOTE_IRD_MISS The event occurs when an instruction read request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile. all
COH_INV_HIT The event occurs when a coherence invalidation is received from another Tile off the VDN and hits the level 2 cache. all
VIC_WB_CNT The event occurs when a cache writeback to main memory, including victim writes or explicit flushes, leaves the Tile. all
TDN_STARVED The event occurs when a snoop is received and the controller enters the TDN starved condition. all
DMA_STARVED The event occurs when a DMA is received and the controller enters the starved condition. all
MDN_STARVED The event occurs when the controller enters the MDN or VDN starved condition. all
RTF_STARVED The event occurs when the controller enters the re-try FIFO starved condition. all
IREQ_STARVED The event occurs when the controller enters the instruction stream starved condition. all
RRTF_STARVED The event occurs when the controller enters the remote re-try FIFO starved condition. all
UDN_PKT_SNT Main processor finished sending a packet to the UDN. all
UDN_SNT UDN word sent to an output port. Participating ports are selected with the UDN_EVT_PORT_SEL field. all
UDN_BUBBLE Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the UDN_EVT_PORT_SEL field. all
UDN_CONGESTION Out of credit on an output port. Participating ports are selected with the UDN_EVT_PORT_SEL field. all
IDN_PKT_SNT Main processor finished sending a packet to the IDN. all
IDN_SNT IDN word sent to an output port. Participating ports are selected with the IDN_EVT_PORT_SEL field. all
IDN_BUBBLE Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the IDN_EVT_PORT_SEL field. all
IDN_CONGESTION Out of credit on an output port. Participating ports are selected with the IDN_EVT_PORT_SEL field. all
MDN_PKT_SNT Main processor finished sending a packet to the MDN. all
MDN_SNT MDN word sent to an output port. Participating ports are selected with the MDN_EVT_PORT_SEL field. all
MDN_BUBBLE Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the MDN_EVT_PORT_SEL field. all
MDN_CONGESTION Out of credit on an output port. Participating ports are selected with the MDN_EVT_PORT_SEL field. all
TDN_PKT_SNT Main processor finished sending a packet to the TDN. all
TDN_SNT TDN word sent to an output port. Participating ports are selected with the TDN_EVT_PORT_SEL field. all
TDN_BUBBLE Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the TDN_EVT_PORT_SEL field. all
TDN_CONGESTION Out of credit on an output port. Participating ports are selected with the TDN_EVT_PORT_SEL field. all
VDN_PKT_SNT Main processor finished sending a packet to the VDN. all
VDN_SNT VDN word sent to an output port. Participating ports are selected with the VDN_EVT_PORT_SEL field. all
VDN_BUBBLE Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the VDN_EVT_PORT_SEL field. all
VDN_CONGESTION Out of credit on an output port. Participating ports are selected with the VDN_EVT_PORT_SEL field. all
UDN_DMUX_STALL UDN Demux stalled due to buffer full all
IDN_DMUX_STALL IDN Demux stalled due to buffer full all
It is a capital mistake to theorise before one has data. Insensibly one begins to twist facts to suit theories instead of theories to suit facts. - Sherlock Holmes
2014/09/12