Configuration parameters that are dependent on CPU/architecture. More...
|maximum number of counters, up to 4 for Athlon (18 for P4). |
|maximum number of events between interrupts. |
Configuration parameters that are dependent on CPU/architecture.
|#define OP_MAX_COUNTERS 8|
|#define OP_MAX_PERF_COUNT 2147483647UL|
maximum number of events between interrupts.
Counters are 40 bits, but for convenience we only use 32 bits. The top bit is used for overflow detection, so user can set up to (2^31)-1