00001 /** 00002 * @file daemon/opd_ibs.h 00003 * AMD Family10h Instruction Based Sampling (IBS) handling. 00004 * 00005 * @remark Copyright 2008-2010 OProfile authors 00006 * @remark Read the file COPYING 00007 * 00008 * @author Jason Yeh <jason.yeh@amd.com> 00009 * @author Paul Drongowski <paul.drongowski@amd.com> 00010 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> 00011 * Copyright (c) 2008 Advanced Micro Devices, Inc. 00012 */ 00013 00014 #ifndef OPD_IBS_H 00015 #define OPD_IBS_H 00016 00017 #include <stdint.h> 00018 00019 #include "opd_ibs_macro.h" 00020 00021 struct transient; 00022 struct opd_event; 00023 00024 /** 00025 * IBS information is processed in two steps. The first step decodes 00026 * hardware-level IBS information and saves it in decoded form. The 00027 * second step translates the decoded IBS information into IBS derived 00028 * events. IBS information is tallied and is reported as derived events. 00029 */ 00030 00031 struct ibs_sample { 00032 struct ibs_fetch_sample * fetch; 00033 struct ibs_op_sample * op; 00034 }; 00035 00036 /** 00037 * This struct represents the hardware-level IBS fetch information. 00038 * Each field corresponds to a model-specific register (MSR.) See the 00039 * BIOS and Kernel Developer's Guide for AMD Model Family 10h Processors 00040 * for further details. 00041 */ 00042 struct ibs_fetch_sample { 00043 unsigned long int rip; 00044 /* MSRC001_1030 IBS Fetch Control Register */ 00045 unsigned int ibs_fetch_ctl_low; 00046 unsigned int ibs_fetch_ctl_high; 00047 /* MSRC001_1031 IBS Fetch Linear Address Register */ 00048 unsigned int ibs_fetch_lin_addr_low; 00049 unsigned int ibs_fetch_lin_addr_high; 00050 /* MSRC001_1032 IBS Fetch Physical Address Register */ 00051 unsigned int ibs_fetch_phys_addr_low; 00052 unsigned int ibs_fetch_phys_addr_high; 00053 unsigned int dummy_event; 00054 }; 00055 00056 00057 00058 /** This struct represents the hardware-level IBS op information. */ 00059 struct ibs_op_sample { 00060 unsigned long int rip; 00061 /* MSRC001_1034 IBS Op Logical Address Register */ 00062 unsigned int ibs_op_lin_addr_low; 00063 unsigned int ibs_op_lin_addr_high; 00064 /* MSRC001_1035 IBS Op Data Register */ 00065 unsigned int ibs_op_data1_low; 00066 unsigned int ibs_op_data1_high; 00067 /* MSRC001_1036 IBS Op Data 2 Register */ 00068 unsigned int ibs_op_data2_low; 00069 unsigned int ibs_op_data2_high; 00070 /* MSRC001_1037 IBS Op Data 3 Register */ 00071 unsigned int ibs_op_data3_low; 00072 unsigned int ibs_op_data3_high; 00073 /* MSRC001_1038 IBS DC Linear Address */ 00074 unsigned int ibs_op_ldst_linaddr_low; 00075 unsigned int ibs_op_ldst_linaddr_high; 00076 /* MSRC001_1039 IBS DC Physical Address */ 00077 unsigned int ibs_op_phys_addr_low; 00078 unsigned int ibs_op_phys_addr_high; 00079 /* MSRC001_103B IBS Branch Target Address */ 00080 unsigned long ibs_op_brtgt_addr; 00081 }; 00082 00083 00084 /** 00085 * Handle an IBS fetch sample escape code sequence. An IBS fetch sample 00086 * is represented as an escape code sequence. (See the comment for the 00087 * function code_ibs_op_sample() for the sequence of entries in the event 00088 * buffer.) When this function is called, the ESCAPE_CODE and IBS_FETCH_CODE 00089 * have already been removed from the event buffer. Thus, 7 more event buffer 00090 * entries are needed in order to process a complete IBS fetch sample. 00091 */ 00092 extern void code_ibs_fetch_sample(struct transient * trans); 00093 00094 /** 00095 * Handle an IBS op sample escape code sequence. An IBS op sample 00096 * is represented as an escape code sequence: 00097 * 00098 * IBS fetch IBS op 00099 * --------------- ---------------- 00100 * ESCAPE_CODE ESCAPE_CODE 00101 * IBS_FETCH_CODE IBS_OP_CODE 00102 * Offset Offset 00103 * IbsFetchLinAd low IbsOpRip low <-- Logical (virtual) RIP 00104 * IbsFetchLinAd high IbsOpRip high <-- Logical (virtual) RIP 00105 * IbsFetchCtl low IbsOpData low 00106 * IbsFetchCtl high IbsOpData high 00107 * IbsFetchPhysAd low IbsOpData2 low 00108 * IbsFetchPhysAd high IbsOpData2 high 00109 * IbsOpData3 low 00110 * IbsOpData3 high 00111 * IbsDcLinAd low 00112 * IbsDcLinAd high 00113 * IbsDcPhysAd low 00114 * IbsDcPhysAd high 00115 * 00116 * When this function is called, the ESCAPE_CODE and IBS_OP_CODE have 00117 * already been removed from the event buffer. Thus, 13 more event buffer 00118 * entries are needed to process a complete IBS op sample. 00119 * 00120 * The IbsFetchLinAd and IbsOpRip are the linear (virtual) addresses 00121 * that were generated by the IBS hardware. These addresses are mapped 00122 * into the offset. 00123 */ 00124 extern void code_ibs_op_sample(struct transient * trans); 00125 00126 /** Log the specified IBS derived event. */ 00127 extern void opd_log_ibs_event(unsigned int event, struct transient * trans); 00128 00129 /** Log the specified IBS cycle count. */ 00130 extern void opd_log_ibs_count(unsigned int event, struct transient * trans, unsigned int count); 00131 00132 00133 #endif /*OPD_IBS_H*/
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