This is a list of all Core 2 CPU's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A. Oprofile use syntethised events and doen't provide a low-level access to Core 2 hardware, so the Intel manual is usefull mainly for people trying to add new events in Oprofile rather for end-user.
| Name | Description | Counters usable | Unit mask options |
| CPU_CLK_UNHALTED | Clock cycles when not halted | all |
0x00: Unhalted core cycles
0x01: Unhalted bus cycles 0x02: Unhalted bus cycles of this core while the other core is halted |
| INST_RETIRED_ANY_P | number of instructions retired | all | |
| L2_RQSTS | number of L2 cache requests | all |
0xc0: core: all cores
0x40: core: this core 0x30: prefetch: all inclusive 0x10: prefetch: Hardware prefetch only 0x00: prefetch: exclude hardware prefetch 0x08: (M)ESI: Modified 0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| LLC_MISSES | L2 cache demand requests from this core that missed the L2 | all |
0x41: No unit mask
|
| LLC_REFS | L2 cache demand requests from this core | all |
0x4f: No unit mask
|
| LOAD_BLOCK | events pertaining to loads | all |
0x02: STA Loads blocked by a preceding store with unknown address.
0x04: STD Loads blocked by a preceding store with unknown data. 0x08: OVERLAP_STORE Loads that partially overlap an earlier store, or 4K aliased with a previous store. 0x10: UNTIL_RETIRE Loads blocked until retirement. 0x20: L1D Loads blocked by the L1 data cache. |
| STORE_BLOCK | events pertaining to stores | all |
0x01: SB_DRAIN_CYCLES Cycles while stores are blocked due to store buffer drain.
0x02: ORDER Cycles while store is waiting for a preceding store to be globally observed. 0x08: NOOP A store is blocked due to a conflict with an external or internal snoop. |
| MISALIGN_MEM_REF | number of misaligned data memory references | all | |
| SEGMENT_REG_LOADS | number of segment register loads | all | |
| SSE_PRE_EXEC | number of SSE pre-fetch/weakly ordered insns retired | all |
0x00: prefetch NTA instructions executed.
0x01: prefetch T1 instructions executed. 0x02: prefetch T1 and T2 instructions executed. 0x03: SSE weakly-ordered stores |
| DTLB_MISSES | DTLB miss events | all |
0x01: ANY Memory accesses that missed the DTLB.
0x02: MISS_LD DTLB misses due to load operations. 0x04: L0_MISS_LD L0 DTLB misses due to load operations. 0x08: MISS_ST TLB misses due to store operations. |
| MEMORY_DISAMBIGUATION | Memory disambiguation reset cycles. | all |
0x01: RESET Memory disambiguation reset cycles.
0x02: SUCCESS Number of loads that were successfully disambiguated. |
| PAGE_WALKS | Page table walk events | all |
0x01: COUNT Number of page-walks executed.
0x02: CYCLES Duration of page-walks in core cycles. |
| FLOPS | number of FP computational micro-ops executed | all | |
| FP_ASSIST | number of FP assists | all | |
| MUL | number of multiplies | all | |
| DIV | number of divides | all | |
| CYCLES_DIV_BUSY | cycles divider is busy | all | |
| IDLE_DURING_DIV | cycles divider is busy and all other execution units are idle. | all | |
| DELAYED_BYPASS | Delayed bypass events | all |
0x00: FP Delayed bypass to FP operation.
0x01: SIMD Delayed bypass to SIMD operation. 0x02: LOAD Delayed bypass to load operation. |
| L2_ADS | Cycles the L2 address bus is in use. | all |
0xc0: All cores
0x40: This core |
| L2_DBUS_BUSY_RD | Cycles the L2 transfers data to the core. | all |
0xc0: All cores
0x40: This core |
| L2_LINES_IN | number of allocated lines in L2 | all |
0xc0: core: all cores
0x40: core: this core 0x30: prefetch: all inclusive 0x10: prefetch: Hardware prefetch only 0x00: prefetch: exclude hardware prefetch |
| L2_M_LINES_IN | number of modified lines allocated in L2 | all |
0xc0: All cores
0x40: This core |
| L2_LINES_OUT | number of recovered lines from L2 | all |
0xc0: core: all cores
0x40: core: this core 0x30: prefetch: all inclusive 0x10: prefetch: Hardware prefetch only 0x00: prefetch: exclude hardware prefetch |
| L2_M_LINES_OUT | number of modified lines removed from L2 | all |
0xc0: core: all cores
0x40: core: this core 0x30: prefetch: all inclusive 0x10: prefetch: Hardware prefetch only 0x00: prefetch: exclude hardware prefetch |
| L2_IFETCH | number of L2 cacheable instruction fetches | all |
0xc0: core: all cores
0x40: core: this core 0x08: (M)ESI: Modified 0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| L2_LD | number of L2 data loads | all |
0xc0: core: all cores
0x40: core: this core 0x30: prefetch: all inclusive 0x10: prefetch: Hardware prefetch only 0x00: prefetch: exclude hardware prefetch 0x08: (M)ESI: Modified 0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| L2_ST | number of L2 data stores | all |
0xc0: core: all cores
0x40: core: this core 0x08: (M)ESI: Modified 0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| L2_LOCK | number of locked L2 data accesses | all |
0xc0: core: all cores
0x40: core: this core 0x08: (M)ESI: Modified 0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| L2_REJECT_BUSQ | Rejected L2 cache requests | all |
0xc0: core: all cores
0x40: core: this core 0x30: prefetch: all inclusive 0x10: prefetch: Hardware prefetch only 0x00: prefetch: exclude hardware prefetch 0x08: (M)ESI: Modified 0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| L2_NO_REQ | Cycles no L2 cache requests are pending | all |
0xc0: All cores
0x40: This core |
| EIST_TRANS_ALL | Intel(tm) Enhanced SpeedStep(r) Technology transitions | all | |
| THERMAL_TRIP | Number of thermal trips | all |
0xc0: No unit mask
|
| L1D_CACHE_LD | L1 cacheable data read operations | all |
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| L1D_CACHE_ST | L1 cacheable data write operations | all |
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| L1D_CACHE_LOCK | L1 cacheable lock read operations | all |
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive 0x02: ME(S)I: Shared 0x01: MES(I): Invalid |
| L1D_CACHE_LOCK_DURATION | Duration of L1 data cacheable locked operations | all |
0x10: No unit mask
|
| L1D_ALL_REF | All references to the L1 data cache | all |
0x10: No unit mask
|
| L1D_ALL_CACHE_REF | L1 data cacheable reads and writes | all |
0x02: No unit mask
|
| L1D_REPL | Cache lines allocated in the L1 data cache | all |
0x0f: No unit mask
|
| L1D_M_REPL | Modified cache lines allocated in the L1 data cache | all | |
| L1D_M_EVICT | Modified cache lines evicted from the L1 data cache | all | |
| L1D_PEND_MISS | Total number of outstanding L1 data cache misses at any cycle | all | |
| L1D_SPLIT | Cache line split load/stores | all |
0x01: split loads
0x02: split stores |
| SSE_PREF_MISS | SSE instructions that missed all caches | all |
0x00: PREFETCHNTA
0x01: PREFETCHT0 0x02: PREFETCHT1/PREFETCHT2 |
| LOAD_HIT_PRE | Load operations conflicting with a software prefetch to the same address | all | |
| L1D_PREFETCH | L1 data cache prefetch requests | all |
0x10: No unit mask
|
| BUS_REQ_OUTSTANDING | Outstanding cacheable data read bus requests duration | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_BNR_DRV | Number of Bus Not Ready signals asserted | all |
0x00: this agent
0x20: include all agents |
| BUS_DRDY_CLOCKS | Bus cycles when data is sent on the bus | all |
0x00: this agent
0x20: include all agents |
| BUS_LOCK_CLOCKS | Bus cycles when a LOCK signal is asserted | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_DATA_RCV | Bus cycles while processor receives data | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_BRD | Burst read bus transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_RFO | number of completed read for ownership transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_WB | number of explicit writeback bus transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_IFETCH | number of instruction fetch transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_INVAL | number of invalidate transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_PWR | number of partial write bus transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRANS_P | number of partial bus transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRANS_IO | number of I/O bus transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRANS_DEF | number of completed defer transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_BURST | number of completed burst transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_MEM | number of completed memory transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_TRAN_ANY | number of any completed bus transactions | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| EXT_SNOOP | External snoops | all |
0x00: bus: this agent
0x20: bus: include all agents 0x08: snoop: HITM snoops 0x02: snoop: HIT snoops 0x01: snoop: CLEAN snoops |
| CMP_SNOOP | L1 data cache is snooped by other core | all |
0xc0: core: all cores
0x40: core: this core 0x01: snoop: CMP2I snoops 0x02: snoop: CMP2S snoops |
| BUS_HIT_DRV | HIT signal asserted | all |
0x00: this agent
0x20: include all agents |
| BUS_HITM_DRV | HITM signal asserted | all |
0x00: this agent
0x20: include all agents |
| BUSQ_EMPTY | Bus queue is empty | all |
0xc0: All cores
0x40: This core |
| SNOOP_STALL_DRV | Bus stalled for snoops | all |
0xc0: core: all cores
0x40: core: this core 0x00: bus: this agent 0x20: bus: include all agents |
| BUS_IO_WAIT | IO requests waiting in the bus queue | all |
0xc0: All cores
0x40: This core |
| L1I_READS | number of instruction fetches | all | |
| L1I_MISSES | number of instruction fetch misses | all | |
| ITLB | number of ITLB misses | all |
0x02: ITLB small page misses
0x10: ITLB large page misses 0x40: ITLB flushes |
| INST_QUEUE_FULL | cycles during which the instruction queue is full | all |
0x02: No unit mask
|
| IFU_MEM_STALL | cycles instruction fetch pipe is stalled | all | |
| ILD_STALL | cycles instruction length decoder is stalled | all | |
| BR_INST_EXEC | Branch instructions executed (not necessarily retired) | all | |
| BR_MISSP_EXEC | Branch instructions executed that were mispredicted at execution | all | |
| BR_BAC_MISSP_EXEC | Branch instructions executed that were mispredicted at Front End (BAC) | all | |
| BR_CND_EXEC | Conditional Branch instructions executed | all | |
| BR_CND_MISSP_EXEC | Conditional Branch instructions executed that were mispredicted | all | |
| BR_IND_EXEC | Indirect Branch instructions executed | all | |
| BR_IND_MISSP_EXEC | Indirect Branch instructions executed that were mispredicted | all | |
| BR_RET_EXEC | Return Branch instructions executed | all | |
| BR_RET_MISSP_EXEC | Return Branch instructions executed that were mispredicted at Execution | all | |
| BR_RET_BAC_MISSP_EXEC | Branch instructions executed that were mispredicted at Front End (BAC) | all | |
| BR_CALL_EXEC | CALL instruction executed | all | |
| BR_CALL_MISSP_EXEC | CALL instruction executed and miss predicted | all | |
| BR_IND_CALL_EXEC | Indirect CALL instruction executed | all | |
| BR_TKN_BUBBLE_1 | Branch predicted taken with bubble 1 | all | |
| BR_TKN_BUBBLE_2 | Branch predicted taken with bubble 2 | all | |
| RS_UOPS_DISPATCHED | Micro-ops dispatched for execution | all | |
| RS_UOPS_DISPATCHED_NONE | No Micro-ops dispatched for execution | all | |
| MACRO_INSTS | instructions decoded | all |
0x01: Instructions decoded
0x08: CISC Instructions decoded |
| ESP | ESP register events | all |
0x01: ESP register content synchronizations
0x02: ESP register automatic additions |
| SIMD_UOPS_EXEC | SIMD micro-ops executed (excluding stores) | all | |
| SIMD_SAT_UOP_EXEC | number of SIMD saturating instructions executed | all | |
| SIMD_UOP_TYPE_EXEC | number of SIMD packing instructions | all |
0x01: SIMD packed multiplies
0x02: SIMD packed shifts 0x04: SIMD pack operations 0x08: SIMD unpack operations 0x10: SIMD packed logical 0x20: SIMD packed arithmetic 0x3f: all of the above |
| INST_RETIRED | number of instructions retired | all |
0x00: Any
0x01: Loads 0x02: Stores 0x04: Other |
| X87_OPS_RETIRED | number of computational FP operations retired | all |
0x01: FXCH instructions retired
0xfe: Retired floating-point computational operations (precise) |
| UOPS_RETIRED | number of UOPs retired | all |
0x01: Fused load+op or load+indirect branch retired
0x02: Fused store address + data retired 0x04: Retired instruction pairs fused into one micro-op 0x07: Fused micro-ops retired 0x08: Non-fused micro-ops retired 0x0f: Micro-ops retired |
| MACHINE_NUKES_SMC | number of pipeline flushing events | all |
0x01: Self-Modifying Code detected
0x04: Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction |
| BR_INST_RETIRED | number of branch instructions retired | all |
0x01: predicted not-taken
0x02: mispredicted not-taken 0x04: predicted taken 0x08: mispredicted taken |
| BR_MISS_PRED_RETIRED | number of mispredicted branches retired (precise) | all | |
| CYCLES_INT_MASKED | cycles interrupts are disabled | all |
0x01: Interrupts disabled
0x02: Interrupts pending and disabled |
| SIMD_INST_RETIRED | SSE/SSE2 instructions retired | all |
0x01: Retired SSE packed-single instructions
0x02: Retired SSE scalar-single instructions 0x04: Retired SSE2 packed-double instructions 0x08: Retired SSE2 scalar-double instructions 0x10: Retired SSE2 vector integer instructions 0x1f: Retired Streaming SIMD instructions (precise event) |
| HW_INT_RCV | number of hardware interrupts received | all | |
| ITLB_MISS_RETIRED | Retired instructions that missed the ITLB | 0 | |
| SIMD_COMP_INST_RETIRED | Retired computational SSE/SSE2 instructions | all |
0x01: Retired computational SSE packed-single instructions
0x02: Retired computational SSE scalar-single instructions 0x04: Retired computational SSE2 packed-double instructions 0x08: Retired computational SSE2 scalar-double instructions |
| MEM_LOAD_RETIRED | Retired loads | 0 |
0x01: Retired loads that miss the L1 data cache (precise event)
0x02: L1 data cache line missed by retired loads (precise event) 0x04: Retired loads that miss the L2 cache (precise event) 0x08: L2 cache line missed by retired loads (precise event) 0x10: Retired loads that miss the DTLB (precise event) |
| FP_MMX_TRANS | MMX-floating point transitions | all |
0x01: float->MMX transitions
0x02: MMX->float transitions |
| MMX_ASSIST | number of EMMS instructions executed | all | |
| SIMD_INSTR_RET | number of SIMD instructions retired | all | |
| SIMD_SAT_INSTR_RET | number of saturated arithmetic instructions retired | all | |
| RAT_STALLS | Partial register stall cycles | all |
0x01: ROB read port
0x02: Partial register 0x04: Flag 0x08: FPU status word 0x0f: All RAT |
| SEG_RENAME_STALLS | Segment rename stalls | all |
0x01: ES
0x02: DS 0x04: FS 0x08: GS |
| SEG_RENAMES | Segment renames | all |
0x01: ES
0x02: DS 0x04: FS 0x08: GS |
| RESOURCE_STALLS | Cycles during which resource stalls occur | all |
0x01: when the ROB is full
0x02: during which the RS is full 0x04: during which the pipeline has exceeded the load or store limit or is waiting to commit all stores 0x08: due to FPU control word write 0x10: due to branch misprediction |
| BR_INST_DECODED | number of branch instructions decoded | all | |
| BR_BOGUS | number of bogus branches | all | |
| BACLEARS | number of times BACLEAR is asserted | all | |
| PREF_RQSTS_UP | Number of upward prefetches issued | all | |
| PREF_RQSTS_DN | Number of downward prefetches issued | all |
Measurement is a crucial component of performance improvement since reasoning and intuition are fallible guides and must be supplemented with tools like timing commands and profilers.- The Practice of Programming, Brian W. Kernighan and Rob Pike