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Intel Core 2 events

This is a list of all Core 2 CPU's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A. Oprofile use syntethised events and doen't provide a low-level access to Core 2 hardware, so the Intel manual is usefull mainly for people trying to add new events in Oprofile rather for end-user.

NameDescriptionCounters usableUnit mask options
CPU_CLK_UNHALTED Clock cycles when not halted 0, 1 0x00: Unhalted core cycles
0x01: Unhalted bus cycles
0x02: Unhalted bus cycles of this core while the other core is halted
INST_RETIRED_ANY_P number of instructions retired 0, 1
L2_RQSTS number of L2 cache requests 0, 1 0xc0: core: all cores
0x40: core: this core
0x30: prefetch: all inclusive
0x10: prefetch: Hardware prefetch only
0x00: prefetch: exclude hardware prefetch
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
LLC_MISSES L2 cache demand requests from this core that missed the L2 0, 1 0x41: No unit mask
LLC_REFS L2 cache demand requests from this core 0, 1 0x4f: No unit mask
LOAD_BLOCK events pertaining to loads 0, 1 0x02: (name=STA) Loads blocked by a preceding store with unknown address.
0x04: (name=STD) Loads blocked by a preceding store with unknown data.
0x08: (name=OVERLAP_STORE) Loads that partially overlap an earlier store, or 4K aliased with a previous store.
0x10: (name=UNTIL_RETIRE) Loads blocked until retirement.
0x20: (name=L1D) Loads blocked by the L1 data cache.
STORE_BLOCK events pertaining to stores 0, 1 0x01: (name=SB_DRAIN_CYCLES) Cycles while stores are blocked due to store buffer drain.
0x02: (name=ORDER) Cycles while store is waiting for a preceding store to be globally observed.
0x08: (name=NOOP) A store is blocked due to a conflict with an external or internal snoop.
MISALIGN_MEM_REF number of misaligned data memory references 0, 1
SEGMENT_REG_LOADS number of segment register loads 0, 1
SSE_PRE_EXEC number of SSE pre-fetch/weakly ordered insns retired 0, 1 0x00: prefetch NTA instructions executed.
0x01: prefetch T1 instructions executed.
0x02: prefetch T1 and T2 instructions executed.
0x03: SSE weakly-ordered stores
DTLB_MISSES DTLB miss events 0, 1 0x01: (name=ANY) Memory accesses that missed the DTLB.
0x02: (name=MISS_LD) DTLB misses due to load operations.
0x04: (name=L0_MISS_LD) L0 DTLB misses due to load operations.
0x08: (name=MISS_ST) TLB misses due to store operations.
MEMORY_DISAMBIGUATION Memory disambiguation reset cycles. 0, 1 0x01: (name=RESET) Memory disambiguation reset cycles.
0x02: (name=SUCCESS) Number of loads that were successfully disambiguated.
PAGE_WALKS Page table walk events 0, 1 0x01: (name=COUNT) Number of page-walks executed.
0x02: (name=CYCLES) Duration of page-walks in core cycles.
FLOPS number of FP computational micro-ops executed 0, 1
FP_ASSIST number of FP assists 0, 1
MUL number of multiplies 0, 1
DIV number of divides 0, 1
CYCLES_DIV_BUSY cycles divider is busy 0, 1
IDLE_DURING_DIV cycles divider is busy and all other execution units are idle. 0, 1
DELAYED_BYPASS Delayed bypass events 0, 1 0x00: (name=FP) Delayed bypass to FP operation.
0x01: (name=SIMD) Delayed bypass to SIMD operation.
0x02: (name=LOAD) Delayed bypass to load operation.
L2_ADS Cycles the L2 address bus is in use. 0, 1 0xc0: All cores
0x40: This core
L2_DBUS_BUSY_RD Cycles the L2 transfers data to the core. 0, 1 0xc0: All cores
0x40: This core
L2_LINES_IN number of allocated lines in L2 0, 1 0xc0: core: all cores
0x40: core: this core
0x30: prefetch: all inclusive
0x10: prefetch: Hardware prefetch only
0x00: prefetch: exclude hardware prefetch
L2_M_LINES_IN number of modified lines allocated in L2 0, 1 0xc0: All cores
0x40: This core
L2_LINES_OUT number of recovered lines from L2 0, 1 0xc0: core: all cores
0x40: core: this core
0x30: prefetch: all inclusive
0x10: prefetch: Hardware prefetch only
0x00: prefetch: exclude hardware prefetch
L2_M_LINES_OUT number of modified lines removed from L2 0, 1 0xc0: core: all cores
0x40: core: this core
0x30: prefetch: all inclusive
0x10: prefetch: Hardware prefetch only
0x00: prefetch: exclude hardware prefetch
L2_IFETCH number of L2 cacheable instruction fetches 0, 1 0xc0: core: all cores
0x40: core: this core
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
L2_LD number of L2 data loads 0, 1 0xc0: core: all cores
0x40: core: this core
0x30: prefetch: all inclusive
0x10: prefetch: Hardware prefetch only
0x00: prefetch: exclude hardware prefetch
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
L2_ST number of L2 data stores 0, 1 0xc0: core: all cores
0x40: core: this core
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
L2_LOCK number of locked L2 data accesses 0, 1 0xc0: core: all cores
0x40: core: this core
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
L2_REJECT_BUSQ Rejected L2 cache requests 0, 1 0xc0: core: all cores
0x40: core: this core
0x30: prefetch: all inclusive
0x10: prefetch: Hardware prefetch only
0x00: prefetch: exclude hardware prefetch
0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
L2_NO_REQ Cycles no L2 cache requests are pending 0, 1 0xc0: All cores
0x40: This core
EIST_TRANS_ALL Intel(tm) Enhanced SpeedStep(r) Technology transitions 0, 1
THERMAL_TRIP Number of thermal trips 0, 1 0xc0: No unit mask
L1D_CACHE_LD L1 cacheable data read operations 0, 1 0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
L1D_CACHE_ST L1 cacheable data write operations 0, 1 0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
L1D_CACHE_LOCK L1 cacheable lock read operations 0, 1 0x08: (M)ESI: Modified
0x04: M(E)SI: Exclusive
0x02: ME(S)I: Shared
0x01: MES(I): Invalid
L1D_CACHE_LOCK_DURATION Duration of L1 data cacheable locked operations 0, 1 0x10: No unit mask
L1D_ALL_REF All references to the L1 data cache 0, 1 0x10: No unit mask
L1D_ALL_CACHE_REF L1 data cacheable reads and writes 0, 1 0x02: No unit mask
L1D_REPL Cache lines allocated in the L1 data cache 0, 1 0x0f: No unit mask
L1D_M_REPL Modified cache lines allocated in the L1 data cache 0, 1
L1D_M_EVICT Modified cache lines evicted from the L1 data cache 0, 1
L1D_PEND_MISS Total number of outstanding L1 data cache misses at any cycle 0, 1
L1D_SPLIT Cache line split load/stores 0, 1 0x01: split loads
0x02: split stores
SSE_PREF_MISS SSE instructions that missed all caches 0, 1 0x00: PREFETCHNTA
0x01: PREFETCHT0
0x02: PREFETCHT1/PREFETCHT2
LOAD_HIT_PRE Load operations conflicting with a software prefetch to the same address 0, 1
L1D_PREFETCH L1 data cache prefetch requests 0, 1 0x10: No unit mask
BUS_REQ_OUTSTANDING Outstanding cacheable data read bus requests duration 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_BNR_DRV Number of Bus Not Ready signals asserted 0, 1 0x00: this agent
0x20: include all agents
BUS_DRDY_CLOCKS Bus cycles when data is sent on the bus 0, 1 0x00: this agent
0x20: include all agents
BUS_LOCK_CLOCKS Bus cycles when a LOCK signal is asserted 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_DATA_RCV Bus cycles while processor receives data 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_BRD Burst read bus transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_RFO number of completed read for ownership transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_WB number of explicit writeback bus transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_IFETCH number of instruction fetch transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_INVAL number of invalidate transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_PWR number of partial write bus transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRANS_P number of partial bus transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRANS_IO number of I/O bus transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRANS_DEF number of completed defer transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_BURST number of completed burst transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_MEM number of completed memory transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_ANY number of any completed bus transactions 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
EXT_SNOOP External snoops 0, 1 0x00: bus: this agent
0x20: bus: include all agents
0x08: snoop: HITM snoops
0x02: snoop: HIT snoops
0x01: snoop: CLEAN snoops
CMP_SNOOP L1 data cache is snooped by other core 0, 1 0xc0: core: all cores
0x40: core: this core
0x01: snoop: CMP2I snoops
0x02: snoop: CMP2S snoops
BUS_HIT_DRV HIT signal asserted 0, 1 0x00: this agent
0x20: include all agents
BUS_HITM_DRV HITM signal asserted 0, 1 0x00: this agent
0x20: include all agents
BUSQ_EMPTY Bus queue is empty 0, 1 0xc0: All cores
0x40: This core
SNOOP_STALL_DRV Bus stalled for snoops 0, 1 0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_IO_WAIT IO requests waiting in the bus queue 0, 1 0xc0: All cores
0x40: This core
L1I_READS number of instruction fetches 0, 1
L1I_MISSES number of instruction fetch misses 0, 1
ITLB number of ITLB misses 0, 1 0x02: ITLB small page misses
0x10: ITLB large page misses
0x40: ITLB flushes
INST_QUEUE_FULL cycles during which the instruction queue is full 0, 1 0x02: No unit mask
IFU_MEM_STALL cycles instruction fetch pipe is stalled 0, 1
ILD_STALL cycles instruction length decoder is stalled 0, 1
BR_INST_EXEC Branch instructions executed (not necessarily retired) 0, 1
BR_MISSP_EXEC Branch instructions executed that were mispredicted at execution 0, 1
BR_BAC_MISSP_EXEC Branch instructions executed that were mispredicted at Front End (BAC) 0, 1
BR_CND_EXEC Conditional Branch instructions executed 0, 1
BR_CND_MISSP_EXEC Conditional Branch instructions executed that were mispredicted 0, 1
BR_IND_EXEC Indirect Branch instructions executed 0, 1
BR_IND_MISSP_EXEC Indirect Branch instructions executed that were mispredicted 0, 1
BR_RET_EXEC Return Branch instructions executed 0, 1
BR_RET_MISSP_EXEC Return Branch instructions executed that were mispredicted at Execution 0, 1
BR_RET_BAC_MISSP_EXEC Branch instructions executed that were mispredicted at Front End (BAC) 0, 1
BR_CALL_EXEC CALL instruction executed 0, 1
BR_CALL_MISSP_EXEC CALL instruction executed and miss predicted 0, 1
BR_IND_CALL_EXEC Indirect CALL instruction executed 0, 1
BR_TKN_BUBBLE_1 Branch predicted taken with bubble 1 0, 1
BR_TKN_BUBBLE_2 Branch predicted taken with bubble 2 0, 1
RS_UOPS_DISPATCHED Micro-ops dispatched for execution 0, 1
RS_UOPS_DISPATCHED_NONE No Micro-ops dispatched for execution 0, 1
MACRO_INSTS instructions decoded 0, 1 0x01: Instructions decoded
0x08: CISC Instructions decoded
ESP ESP register events 0, 1 0x01: ESP register content synchronizations
0x02: ESP register automatic additions
SIMD_UOPS_EXEC SIMD micro-ops executed (excluding stores) 0, 1
SIMD_SAT_UOP_EXEC number of SIMD saturating instructions executed 0, 1
SIMD_UOP_TYPE_EXEC number of SIMD packing instructions 0, 1 0x01: SIMD packed multiplies
0x02: SIMD packed shifts
0x04: SIMD pack operations
0x08: SIMD unpack operations
0x10: SIMD packed logical
0x20: SIMD packed arithmetic
0x3f: all of the above
INST_RETIRED number of instructions retired 0, 1 0x00: (name=Any) Any
0x01: (name=Loads) Loads
0x02: (name=Stores) Stores
0x04: (name=Other) Other
X87_OPS_RETIRED number of computational FP operations retired 0, 1 0x01: FXCH instructions retired
0xfe: Retired floating-point computational operations (precise)
UOPS_RETIRED number of UOPs retired 0, 1 0x01: Fused load+op or load+indirect branch retired
0x02: Fused store address + data retired
0x04: Retired instruction pairs fused into one micro-op
0x07: Fused micro-ops retired
0x08: Non-fused micro-ops retired
0x0f: Micro-ops retired
MACHINE_NUKES_SMC number of pipeline flushing events 0, 1 0x01: Self-Modifying Code detected
0x04: Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction
BR_INST_RETIRED number of branch instructions retired 0, 1 0x01: predicted not-taken
0x02: mispredicted not-taken
0x04: predicted taken
0x08: mispredicted taken
BR_MISS_PRED_RETIRED number of mispredicted branches retired (precise) 0, 1
CYCLES_INT_MASKED cycles interrupts are disabled 0, 1 0x01: Interrupts disabled
0x02: Interrupts pending and disabled
SIMD_INST_RETIRED SSE/SSE2 instructions retired 0, 1 0x01: Retired SSE packed-single instructions
0x02: Retired SSE scalar-single instructions
0x04: Retired SSE2 packed-double instructions
0x08: Retired SSE2 scalar-double instructions
0x10: Retired SSE2 vector integer instructions
0x1f: Retired Streaming SIMD instructions (precise event)
HW_INT_RCV number of hardware interrupts received 0, 1
ITLB_MISS_RETIRED Retired instructions that missed the ITLB 0
SIMD_COMP_INST_RETIRED Retired computational SSE/SSE2 instructions 0, 1 0x01: Retired computational SSE packed-single instructions
0x02: Retired computational SSE scalar-single instructions
0x04: Retired computational SSE2 packed-double instructions
0x08: Retired computational SSE2 scalar-double instructions
MEM_LOAD_RETIRED Retired loads 0 0x01: Retired loads that miss the L1 data cache (precise event)
0x02: L1 data cache line missed by retired loads (precise event)
0x04: Retired loads that miss the L2 cache (precise event)
0x08: L2 cache line missed by retired loads (precise event)
0x10: Retired loads that miss the DTLB (precise event)
FP_MMX_TRANS MMX-floating point transitions 0, 1 0x01: float->MMX transitions
0x02: MMX->float transitions
MMX_ASSIST number of EMMS instructions executed 0, 1
SIMD_INSTR_RET number of SIMD instructions retired 0, 1
SIMD_SAT_INSTR_RET number of saturated arithmetic instructions retired 0, 1
RAT_STALLS Partial register stall cycles 0, 1 0x01: ROB read port
0x02: Partial register
0x04: Flag
0x08: FPU status word
0x0f: All RAT
SEG_RENAME_STALLS Segment rename stalls 0, 1 0x01: (name=ES) ES
0x02: (name=DS) DS
0x04: (name=FS) FS
0x08: (name=GS) GS
SEG_RENAMES Segment renames 0, 1 0x01: (name=ES) ES
0x02: (name=DS) DS
0x04: (name=FS) FS
0x08: (name=GS) GS
RESOURCE_STALLS Cycles during which resource stalls occur 0, 1 0x01: when the ROB is full
0x02: during which the RS is full
0x04: during which the pipeline has exceeded the load or store limit or is waiting to commit all stores
0x08: due to FPU control word write
0x10: due to branch misprediction
BR_INST_DECODED number of branch instructions decoded 0, 1
BR_BOGUS number of bogus branches 0, 1
BACLEARS number of times BACLEAR is asserted 0, 1
PREF_RQSTS_UP Number of upward prefetches issued 0, 1
PREF_RQSTS_DN Number of downward prefetches issued 0, 1
Optimizations always bust things, because all optimizations are, in the long haul, a form of cheating, and cheaters eventually get caught. - Larry Wall
2013/07/29